Oversampling correlator with virtual clock phase for a telecommu

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

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H04L 700

Patent

active

056993897

ABSTRACT:
A correlation circuit (200) for detecting a correct phase for data bits in a received data stream includes a clock generator (204) configured to generate a plurality of clock signals, each clock signal having a predetermined unique clock phase. A plurality of data correlators (210, 212, 214, 216, 218, 220) generate respective pass indications when respective unique clock phases are adequate for accurate detection of the data bits in the data stream. In response to the pass indications, a control circuit (206) provides a clock signal for clocking the data. The control circuit (206) includes a delay block (278) and decision logic (270) for selectively delaying one clock phase of the generated plurality of clock phases. The control circuit may provide one of the generated clock phases or a delayed clock phase for clocking the received data.

REFERENCES:
patent: 4458206 (1984-07-01), Dellande et al.
patent: 4821297 (1989-04-01), Bergmann et al.
patent: 4829543 (1989-05-01), Borth et al.
patent: 5022054 (1991-06-01), Wang
patent: 5084891 (1992-01-01), Ariyavisitakul et al.
patent: 5428647 (1995-06-01), Rasky et al.

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