Oversampling clock recovery having a high follow-up...

Details Oversampling clock recovery having a high follow-up... Oversampling clock recovery having a high follow-up...

2006-03-07

2006-03-07

Tse, Young T. (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C370S517000, C327S144000, C327S153000

Reexamination Certificate

active

07010074

ABSTRACT:
An oversampling clock recovery method according to this invention generates non-uniform three-phase clock signals CLKa, CLKb, and CLKc having non-uniform intervals for one bit of an input data i and controls phases of the clock signals so that either phase of two edges of two-phase clock signals CLKb and CLKc having a relatively narrower interval of 57 ps synchronizes with a phase of a transition point of the input data i. By changing clock signals to be phase-locked in three delay locked loops (DLLs), a phase interval of 57 ps is formed.

REFERENCES:
patent: 5633899 (1997-05-01), Fiedler et al.
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6281759 (2001-08-01), Coffey
patent: 6337590 (2002-01-01), Millar
patent: 6483360 (2002-11-01), Nakamura
patent: 6492851 (2002-12-01), Watarai
patent: 9-233061 (1997-09-01), None
patent: 2001-285266 (2001-10-01), None
patent: 2002-50960 (2002-02-01), None

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