Oversampling clock recovery circuit applicable not only to...

Details Oversampling clock recovery circuit applicable not only to... Oversampling clock recovery circuit applicable not only to...

2007-01-23

2007-01-23

Tse, Young T. (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C370S518000, C327S144000

Reexamination Certificate

active

10100871

ABSTRACT:
In an oversampling clock recovery circuit comprising first through fourth phase comparators (PD1to PD4) and a majority circuit (10), DOWN signal output terminals (DN2(out), DN3(out)) of the second and the third phase comparators are connected to UP signal input terminals (UP3(in), UP4(in)) of the majority circuit and UP signal output terminals (UP3(out), UP4(out)) of the third and the fourth phase comparators are connected to DONW signal input terminals (DN2(in), DN3(in)) of the majority circuit.

REFERENCES:
patent: 5301196 (1994-04-01), Ewen et al.
patent: 5633899 (1997-05-01), Fiedler et al.
patent: 6130584 (2000-10-01), Yoshida
patent: 6259755 (2001-07-01), O'Sullivan et al.
patent: 6266799 (2001-07-01), Lee et al.
patent: 6445316 (2002-09-01), Hsu et al.
patent: 0 942 551 (1999-09-01), None
patent: 9-233061 (1997-09-01), None
Inyeol Lee et. al., “A 622 Mb/s CMOS Clock Recovery PLL with Time-Interleaved Phase Detector Array”, IEEE (1996), pp. 198-199 and p. 444.

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