Overmold integrated circuit package

Details Overmold integrated circuit package Overmold integrated circuit package

2001-08-27

2003-02-18

Arbes, Carl J. (Department: 3729)

Metal working

Method of mechanical manufacture

Electrical device making

C029S840000, C257S711000, C257S778000, C257S780000, C257S789000, C438S108000, C438S126000, C438S127000

Reexamination Certificate

active

06519844

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit package manufacturing. More particularly the invention relates to a process for fabricating an overmolded flip chip integrated circuit package.
BACKGROUND
As computing and electronic signal processing devices become increasingly smaller and faster, the demand grows for ever smaller and faster multilayer flip chip integrated circuit packages. As integrated circuits become increasingly faster, they tend to draw a greater amount of current within a given amount of time, thereby generating more heat which must be dissipated within that given amount of time. Further complicating this situation is the trend of ever decreasing size of the integrated circuits. Thus, as new generations of integrated circuits are designed and created, they tend to generate more heat at a faster rate and within a smaller area than prior designs.
If the heat generated by an integrated circuit is not adequately dissipated, the integrated circuit may fail over time, and the failure mode can take many forms. For example, the active devices themselves, such as semiconductor devices, may become too hot and change in fundamental nature, thereby becoming inoperable.
To aid in dissipating heat, a flip chip die may be encapsulated or “overmolded” with an epoxy having good thermal transfer characteristics. The overmolding compound has typically been applied in a molding process, wherein the molding compound is injected over the flip chip and between the flip chip and an underlying substrate.
A problem with the overmolding process that has plagued manufacturers is the tendency for air pockets to be trapped between the flip chip die and the underlying substrate. Such air pockets or voids degrade the effectiveness of the molding compound to transfer heat away from the chip, which may lead to chip overheating and premature failure.
What is needed, therefore, is a process for overmolding a flip chip die while preventing formation of voids between the die and the underlying substrate.
SUMMARY
The above and other needs are met by an integrated circuit package manufacturing process which reduces or eliminates the formation of voids in a molding compound disposed between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. A plurality of vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the plurality of vias and the air space. In this manner, air trapped between the molding compound and the upper surface of the substrate is urged to flow into the vias rather than forming a void in the molding compound.
In various preferred embodiments of the invention, fluid communication between the plurality of vias and the air space is provided by not tenting the vias with a solder mask layer, or by removing any solder mask or other material which may have filled or tented over the vias during prior processing of the substrate.
The invention offers significant advantages over other fabrication processes which involve drilling a hole through the substrate to vent air trapped between the die and the substrate. With the process according to the invention, no valuable substrate real estate is lost to a through hole in the substrate, the substrate cost is not increased by the requirement of drilling a hole during substrate manufacturing, and existing substrate designs do not have to be modified, such as by re-routing traces, to accommodate a through hole in the substrate.


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patent: 5629566 (1997-05-01), Doi et al.
patent: 5818113 (1998-10-01), Iseki et al.
patent: 6218731 (2001-04-01), Huang et al.
patent: 6229215 (2001-05-01), Egawa
patent: 6369449 (2002-04-01), Farquhar et al.
patent: 6406990 (2002-06-01), Kawai

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