Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-01-03
2002-10-22
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
36
Reexamination Certificate
active
06468815
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the manufacture of high performance integrated circuits on semiconductor wafers. More specifically, this invention relates to optimizing the manufacture of high performance integrated circuits on semiconductor wafers. Even more specifically, this invention relates to optimizing the manufacture of high performance integrated circuits on semiconductor wafers by accurately determining the placement errors and reducing the effect of placement errors.
2. Discussion of the Related Art
In the field of defect capture and analysis during the manufacture of integrated circuits on semiconductor wafers, a useful tool for determining the root cause of current layer defects is a method that partitions defects. Partitioning refers to a method of removing defects caught at previous layers from the population of defects at the current layer. It is accomplished by drawing a circle of a given radius around each defect at the current layer and having stacked the current layer with the previous layer's data removing all defects that lie within the circles. This is especially useful for determining equipment related excursions, layer defectivity effects on yield, and layer specific defect issues. Radial based partitioning methodology is well established in a variety of commercial defect and yield data management systems.
In order for partitioning to be effective there must be a high degree of correspondence to defect positioning between several different equipment models and across several manufacturers of defect scanning equipment. Due to a lack of a global alignment marking system, equipment manufacturers have developed a variety of schemes to assign an xy positioning value to caught defects. Typically these schemes are based on the wafer center; other schemes wafer edge or pattern alignments are used. This lack of uniformity of methodology adds error to absolute defect placement. In addition, the inherent inaccuracy of defect placement of dark field scanning tools adds error to positioning.
These placement errors manifest themselves as several different types. There can be offset errors due to scan recipe setup alignment offsets or equipment tool setup offsets or scan stage (wafer holder) offsets. There can be rotational errors due to wafer notch alignment off axis rotational error. In addition, there can be general misplacement error due to equipment error or general lack of equipment precision.
These errors combine to make partitioned data relatively inaccurate, enough so that manufacturing decisions cannot be made reliably with the current data.
Therefore, what is needed is a method of accurately determining the size and direction of these errors and a method of reducing the effects of these errors and offsets during the manufacturing process of semiconductor wafers.
SUMMARY OF THE INVENTION
According to the present invention, the foregoing and other objects and advantages are achieved by a method of reducing the effects of placement errors during defect capture and analysis during the manufacture of integrated devices on semiconductor wafers.
In accordance with an aspect of the present invention, defects from a current layer are evaluated in relation to defects from previous layers.
In accordance with another aspect of the present invention, a placement circle radius is determined by a defect management system based upon expected placement errors.
In accordance with another aspect of the present invention, an oversized overlay map is applied to the current layer defect information.
In accordance with another aspect of the present invention, a best-fit analysis is applied to fit defect data in the placement circles.
In accordance with another aspect of the present invention, the oversized overlay map is reduced to catch defects at a minimum distance.
In accordance with another aspect of the present invention, a trend analysis is performed to determine the type of placement error.
In accordance with another aspect of the present invention, defects are translated to their proper locations.
The described method thus provides a method of accurately determining placement errors and a method of reducing the effects of the placement errors.
The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.
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Steffan Paul J.
Yu Allen S.
Advanced Micro Devices , Inc.
Nelson H. Donald
Niebling John F.
Stevenson André
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