Overlay mark for measuring and correcting alignment errors

Details Overlay mark for measuring and correcting alignment errors Overlay mark for measuring and correcting alignment errors

2007-10-30

2007-10-30

Clark, Jasmine (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C257S620000, C257SE21523, C257SE21524, C257SE23179

Reexamination Certificate

active

10997441

ABSTRACT:
An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.

REFERENCES:
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patent: 6719918 (2004-04-01), Lee et al.
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patent: 01-5118 (2001-01-01), None
patent: 01-46359 (2001-06-01), None

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