Overlapping peripheral chip select space with DRAM on a...

Details Overlapping peripheral chip select space with DRAM on a... Overlapping peripheral chip select space with DRAM on a...

1997-03-07

2001-12-04

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S172000, C711S169000, C711S158000

Reexamination Certificate

active

06327640

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computers and more particularly to addressing of computer peripherals and memories.
2. Description of the Related Art
In a typical microcontroller design, various chip select signals are available that indicate that an address is within a particular address range and can be used to select a particular device. An example of such a microcontroller is the AM186™ES which is compatible with the 80186 microcontroller. Details of one example of a '186 microcontroller can be found in the Advanced Micro Devices data sheets for the AM186™ES (Publication #20002; Rev. A; Amendment/0; Issue Date: January 1996), the Am186™EM and Am188™EM (Publication #19168 Rev. D Amendment /0; Issue Date: January 1996) and the “Am186™EM/188™EM/188™EMUser's Manual with Am 186 Family Instruction Definitions, ” which are incorporated herein by reference.
In the AM186™ES, the available chip selects include an upper memory chip select (UCS). UCS is used for the upper address space and in the AM186™ES has a block size varying from 64 Kbytes to 512 Kbytes and an ending address of FFFFFh. A lower memory chip select (LCS) indicates an address in the lower memory region with a starting address of 00000h In the AM186™ES, the block size for LCS can range from 64 Kbytes to 512 Kbytes. Midrange chip selects with programmable starting addresses and block sizes are also available. The peripheral chip selects (PCS) provide additional capability to select peripheral devices and they can be programmed to reside anywhere in the 1 Mbyte address space of the '186. The block size of the peripheral chip selects is small relative to LCS and UCS and can be e.g., 256 bytes.
However, PCS address space in typical '186 microcontrollers is mutually exclusive with the address space of other chip selects such as LCS or UCS. Thus, if PCS is mapped into the lower or upper address space, large amounts of address space is lost. For example, if PCS is mapped into a 256 byte block starting at address 40000h, then the maximum memory size for LCS is 256 Kbytes (0 to 3FFFF). The address space from 40000-7FFFF can not be used for LCS. Thus, a 256 byte address space for LCS caused the sacrifice of almost 256 Kbytes of address space.
In prior '186 microcontrollers, if PCS address space was overlapped with a UCS (or LCS) address space, several unwanted things could take place. Referring to
FIG. 1
, two devices, such as UCS device
101
and PCS device
103
could try to drive bus
107
simultaneously for a read operation. Further, the devices may have different ready and wait state requirements. Thus, the UCS device may have zero wait states and the PCS device could have 3 wait states. When a chip select (such as PCS, LCS or UCS) is decoded to be active, in some microcontroller implementations, assertion of the chip select causes its ready and wait state programming to be placed onto an internal bus within the microcontroller. If two chip selects are decoded in the same space, the ready and wait states of both devices will drive on the internal bus causing contention and unpredictable behavior.
It would be desirable to overlay PCS address space over LCS or UCS address space without sacrificing large portions of the address space and without causing undesirable and unpredictable results.
SUMMARY OF THE INVENTION
Accordingly, the invention provides a method and apparatus to map a peripheral device selected with a chip select onto address space occupied by DRAM without causing internal or external contentions. Specifically, the invention provides a method which provides a first address range for accessing DRAM. A second address range is provided for accessing another device. The second address range is within the first address range. A row address strobe is provided for accesses to both the first and second address range but the column address strobe to the DRAM is inhibited when a memory access occurs to the second address range.
The invention also provides apparatus including a circuit which receives a first indication signal that is asserted when the address is in a first address range indicating a DRAM access. The circuit also receives a second indication signal that is asserted when the address is in a second address range indicating an access to a peripheral device. The second address range is within the first address range. The circuit provides a column address strobe according to the first indication signal. An inhibiting circuit receives the second indication signal and inhibits assertion of the column address strobe when the second indication signal is asserted. The inhibiting circuit prevents multiple devices driving external buses on read operations. Further, a priority resolution circuit provides priority to the second indication signal for retrieval of communication protocols programming internal to the processor, thus preventing unpredictable contention on internal buses.


REFERENCES:
patent: Re. 36482 (2000-01-01), Baba
patent: 4316248 (1982-02-01), Retter
patent: 4330823 (1982-05-01), Retter
patent: 4675808 (1987-06-01), Grinn et al.
patent: 4811204 (1989-03-01), Fung
patent: 5265231 (1993-11-01), Nuwayser
patent: 5276812 (1994-01-01), Yamada et al.
patent: 5276833 (1994-01-01), Auvinen et al.
patent: 5276858 (1994-01-01), Oak et al.
patent: 5301328 (1994-04-01), Begur et al.
patent: 5309568 (1994-05-01), Ghosh et al.
patent: 5386547 (1995-01-01), Jouppi
patent: 5420995 (1995-05-01), Taguri
patent: 5469559 (1995-11-01), Parks et al.
patent: 5522062 (1996-05-01), Yamaki
patent: 5530837 (1996-06-01), Williams et al.
patent: 5535169 (1996-07-01), Endo et al.
patent: 5559992 (1996-09-01), Stutz et al.
patent: 5590078 (1996-12-01), Chatter
patent: 5623638 (1997-04-01), Andrade
patent: 5634112 (1997-05-01), Thome et al.
patent: 5636367 (1997-06-01), Stones et al.
patent: 5638528 (1997-06-01), Gay et al.
patent: 5649161 (1997-07-01), Andrade et al.
patent: 5664168 (1997-09-01), Yishay et al.
patent: 5668815 (1997-09-01), Gittinger et al.
patent: 5706407 (1998-01-01), Nakamura et al.
patent: 5724604 (1998-03-01), Moyer
patent: 5737744 (1998-04-01), Callison et al.
patent: 5748977 (1998-05-01), Kawasaki et al.
patent: 5751645 (1998-05-01), Tsukikawa
patent: 5781492 (1998-07-01), Gittinger et al.
patent: 5787291 (1998-07-01), Moyer et al.
patent: 5822768 (1998-10-01), Shakkarwar
patent: 5860129 (1999-01-01), Moyer et al.
patent: 5862148 (1999-01-01), Typaldos et al.
patent: 5875451 (1999-02-01), Joseph
patent: 5878268 (1999-03-01), Hagersten
patent: 5937170 (1999-08-01), Bedarida
patent: 5987579 (1999-11-01), Nishtala et al.
Advanced Micro Devices, “Am186™EM and AM188™EM User's Manual with Am186 Instruction Definitions”, 1995, pp. 1-1 thru 1-6; 2-1 thru 2-9; 3-1 thru 3-18; 4-1 thru 4-9; 5-1 thru 5-12; 6-1 thru 6-2; 7-1 thru 7-35; and 12-1 thru 12-6.
Advanced Micro Devices, “Am186™EM and AM188™EM High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers”, 1996, pp. 29-48, 52-68, and 93-96.
Advanced Micro Devices, “Am186™ES and AM188™ES High-Performance, 80C186- and 80C188-Compatible, 16-Bit Embedded Microcontrollers”, 1996, pp. 24-52, and 65-75.

Affiliated with

Also associated with

Rating

Overlapping peripheral chip select space with DRAM on a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Overlapping peripheral chip select space with DRAM on a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Overlapping peripheral chip select space with DRAM on a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2583102