Overlap remover manager

Details Overlap remover manager Overlap remover manager

2002-02-07

2004-03-02

Whitmore, Stacy A (Department: 2812)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06701503

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to the field of integrated circuit design, and particularly to a system and method for providing an overlap manager to reduce timing worsening and avoid ramptime violations in an improved manner when designing an integrated circuit.
BACKGROUND OF THE INVENTION
The integrated circuit (IC) has permeated most every aspect of modern life. From home to business uses, a variety of functions are provided by integrated circuits. To provide this diverse and wide ranging functionality, integrated circuits may be designed for both general uses to provide generalized operation as well as configured in a manner optimized to a given task or set of tasks. Thus, the design of an integrated circuit may take a wide range of configurations.
During the design of an integrated circuit, a timing driven resynthesis procedure may be employed to test whether the design of the integrated circuit complies with contemplated timing parameters. After this procedure is employed, an overlap remover manager may be employed to get a legal placement of the design. Although a timing driven resynthesis procedure may be configured to attempt to place new cells without overflows, overlap of the cells may still be possible. For instance, a design achieved from an overlap remover manager may not have cell overlaps. However, ramptime violations and the timing characteristics of the paths may be worse in general than before the overlap remover manager was utilized.
Therefore, it would be desirable to provide an overlap remover manager.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a system and method for providing an overlap remover manager. In a first aspect of the present invention, a method for removing overlaps in a circuit design for an integrated circuit includes initiating an overlap remover manager, wherein the overlap remover manager is suitable for moving cells of an integrated circuit design to remove cell overlaps. A search for critical wires is performed and a determination is made of which violated moves of cells caused at least one critical wire. A determined violated move of the cells is rolled back and the overlap remover manager employed to remove overlaps between rolled back cells. In a second aspect of the invention, violated cells that were rolled back are fixed and the overlap remover manager run to remove overlaps between rolled back cells and at least one other cell which was not rolled back. If overlaps remain, the cells are unfixed and the overlap remover manager run.
In a third aspect of the present invention, a system for removing overlaps in a circuit design for an integrated circuit includes a memory suitable for storing a program of instruction and a processor communicatively coupled to the memory. The program of instructions configures the processor to initiate an overlap remover manager, wherein the overlap remover manager is suitable for moving cells of a received integrated circuit design to remove cell overlaps. A search for critical wires is performed and a determination is made of which violated moves of cells caused at least one critical wire. A determined violated move of the cells is rolled back and the overlap remover manager employed to remove overlaps between rolled back cells.
It is to be understood that both the forgoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.


REFERENCES:
patent: 6532582 (2003-03-01), Zolotykh et al.
patent: 6543032 (2003-04-01), Zolotykh et al.
patent: 6564361 (2003-05-01), Zolotykh et al.
patent: 2002/0162085 (2002-10-01), Zolotykh et al.

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