Overflow protected first-in first-out architecture

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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C710S057000, C711S154000

Reexamination Certificate

active

10773482

ABSTRACT:
An electronic device (10). The device comprises an input (16I) for receiving successive data words, wherein each data word of the successive data words comprises a plurality of bits. The device also comprises a memory structure (12) comprising a plurality of memory word addresses, wherein each memory word address corresponds to a storage structure operable to store a data word having the plurality of bits. The device also comprises control circuitry (14, 16), operable during a non-overflow condition of the memory structure, for writing successive ones of received data words into respective successive ones of the memory word addresses. Finally, the device also comprises control circuitry (14, 16), operable during an overflow condition of the memory structure, for writing each data word in successive ones of received data words across multiple ones of the memory word addresses.

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patent: 6556495 (2003-04-01), Condorelli et al.
“End-to-End Performance Models For Variable Bit Rate Voice Over Tandem Links In Packet Networks”, S. Dravida & K. Sriram, Infocom '89. Proceedings of the Eighth Annual Joint Conference of the IEEE Computer and Communications Societies. Technology: Emerging or Converging, IEEE Ottawa, Ont., Canada Apr. 23-27, 1989, Washington, DC USA, IEEE Computer Soc. PR, US, pp. 1089-1097, XP010015471, ISBN: 0-8186-1920-1.

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