Overdriven pass transistors

Details Overdriven pass transistors Overdriven pass transistors

2001-06-01

2002-12-31

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000, C326S113000

Reexamination Certificate

active

06501295

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to transistor devices and, more particularly, to pass transistor structures and methods.
BACKGROUND OF THE INVENTION
An important capability in modern electronic systems is the capability for making programmable interconnections between logic components or logic blocks. This capability is provided by components such as Field Programmable Gate Arrays (FPGAs) and other programmable interconnect logic and circuits. Consequently, it is important to find methods to improve performance of these devices, reduce their power consumption and simplify their structures and design.
FIG. 1
is a schematic representation of a typical prior art structure
100
that included: prior art logic block
101
; prior art logic block
103
; and prior art transmission gate
105
, coupled between prior art logic block
101
and prior art logic block
103
. As shown in
FIG. 1
, prior art logic block
101
included input node
111
and output node
113
. Like prior art logic block
101
, prior art logic block
103
also included an input node
119
and output node
121
. Prior art logic blocks
101
and
103
typically comprised any one of numerous devices well known to those of skill in the art such as single transistors, inverters, latches, any one of several gates, or any other logic or memory devices. Both prior art logic blocks
101
and
103
were provided with prior art first supply voltage
131
and prior art second supply voltage
133
. Since prior art logic blocks
101
and
103
were typically standard CMOS, the prior art supply voltage was typically on the order of two volts or more. Consequently, prior art first supply voltage
131
was typically 2.0 volts and prior art second supply voltage
133
was typically ground.
As seen in
FIG. 1
, prior art structure
100
also included prior art transmission gate
105
for selectively, and programmably, connecting prior art logic blocks
101
and
103
. Prior art transmission gate
105
included first node
115
, coupled to output node
113
of prior art logic gate
101
, and second node
117
, coupled to input node
119
of prior art logic block
103
. Prior art transmission gate
105
also included: prior art NFET
107
with gate
107
G and prior art PFET
109
with gate
109
G. Prior art NFET
107
and prior art PFET
109
were typically coupled together as shown in
FIG. 1
, to allow transmission of both digital one and digital zero values as discussed in more detail below.
Prior art transmission gate
105
had three significant drawbacks. First, the addition of prior art transmission gate
105
added significant resistance to the path between output node
113
of prior art logic block
101
and input node
119
of prior art logic block
103
, i.e., prior art transistors
107
and
109
each added a resistance in series to the path between prior art logic block
101
and prior art logic block
103
. Second, prior art transmission gate
105
was a relatively complex structure requiring the use of at least two transistors,
107
and
109
. Third, prior art transmission gate
105
added significant parasitic capacitance to the path between output node
113
of prior art logic block
101
and input node
119
of prior art logic block
103
. The added resistance and parasitic capacitance meant decreased performance of prior art structure
100
and increased power dissipation. The performance reduction due to the addition of prior art transmission gate
105
, and prior art transistors
107
and
109
, could be partially offset in the prior art by increasing the size of prior art transistors
107
and
109
relative to the size of the transistors making up logic blocks
101
and
103
(not shown). However, even a ten fold increase in relative size of prior art transistors
107
and
109
, compared to the transistors in logic blocks
101
and
103
, would still typically yield a decrease in performance of more than ten percent. This was still a very significant performance loss.
A theoretical way to minimize the decrease in performance of prior art structure
100
due to the addition of prior art transistors
107
and
109
would be to drive prior art transistors
107
and
109
at a higher voltage than the voltage driving logic blocks
101
and
103
. However, in practice, to actually make any significant difference in the performance, i.e., to significantly decrease the resistance added by prior art transistors
107
and
109
, the supply voltages of prior art gating transistors
107
and
109
would need to be multiples, and preferably an order of magnitude, larger than the differential between first supply voltage
131
and second supply voltage
133
. However, as noted above, in standard CMOS, the voltage differential between first supply voltage
131
and second supply voltage
133
is on the order of two volts. Standard transistors typically cannot tolerate more than about 2.5 volts in 0.25 micron technology with 50 angstroms of gate oxide, consequently, the voltage differential required to significantly decrease the added resistance of prior art transistors
107
and
109
could not be withstood by standard CMOS transistors, over time, and prior art transistors
107
and
109
would eventually break down.
The relative complexity of prior art transmission gate
105
, i.e., the need for two prior art transistors
107
and
109
, arose from the relatively high threshold voltages of prior art transistors
107
and
109
and from the well known body effect. As a result, NFETs, such as prior art transistor
107
, could pass a digital zero relatively well but could not pass a digital one efficiently. On the other hand, PFETs, such as prior art transistor
109
could pass a digital one relatively well but could not pass a digital zero well. Consequently, in prior art transmission gates, such as prior art transmission gate
105
, an NFET, such as prior art transistor
107
, was included to pass digital zeros while a PFET, such as prior art transistor
109
was included in transmission gate
105
to pass digital ones. This coupling of NFETs and PFETs performed reasonably well in prior art transmission gates
105
. However, the use of two transistors
107
and
109
meant increased parasitic capacitance, increased area, and increased circuit complexity, with more elements to potentially fail.
What is needed is a method and apparatus for providing a transmission gate function between two logic blocks that is more efficient, in terms of lowering added resistance, lowering added parasitic capacitance and in terms of circuit complexity and size.
SUMMARY OF THE INVENTION
According to one embodiment of the invention, low voltage programmable logic structures are provided that include low voltage logic blocks comprised of low threshold transistors. The low voltage logic blocks are provided with low supply voltages. According to one embodiment of the invention, the low voltage logic blocks are separated by pass transistors. Since the logic blocks of the invention are low voltage, the pass transistors of the invention can be overdriven on, i.e., provided gate to source voltages (Vgs) significantly larger than the programmable logic structure's supply voltage, without causing the destruction of the pass transistor. For instance, in one embodiment of the invention, the programmable logic structure's supply voltage is 200 millivolts while the gate to source voltage (V
gs
) of the pass transistor, when the transistor is overdriven on, is on the order of 2.0 volts. This is in direct contrast to prior art transmission gates that had to be driven at essentially the same V
gs
as the supply voltage to avoid transistor breakdown. By overdriving the pass transistors of the invention, the resistance added to the structure by the pass transistors, i.e., the resistance added by coupling the pass transistor between logic blocks is decreased significantly without resorting to increasing the size of the pass transistors.
In addition, if even less resistance is desired, the size of the pass transistors of th

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