Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1997-07-23
2001-04-10
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S086000, C327S112000, C327S390000
Reexamination Certificate
active
06215329
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a pull-up/pull-down output stage suitable for low supply-voltage applications. More particularly, the present invention relates to an output stage for an electronic memory device and for low supply-voltage applications and of the type that includes a final stage of the pull-up/pull-down type made up of a complementary pair of transistors inserted between a primary reference supply voltage and a secondary reference voltage, and a voltage regulator for the control terminals of these transistors.
2. Discussion of the Related Art
As known, the function fulfilled by an output buffer stage of a memory device is to supply to the exterior of the device data taken during a reading operation of a memory cell.
Normally, a memory device presents at its output a load consisting of a large load capacitor Cload (usually 100 pF).
The load capacitor Cload is charged or discharged depending on whether the cell read is written or virgin.
A conventional method of performing this operation is described with reference to
FIG. 1
in which reference number
1
indicates as a whole the output stage of a memory device. This stage
1
comprises a load capacitor Cload connected downstream of a final stage
2
of the pull-up/pull-down type.
Specifically the load capacitor Cload is charged by a pull-up transistor
3
and discharged by a pull-down transistor
4
.
The final stage
2
is connected downstream of a control logic
5
and has an output terminal
6
.
Since the output buffer
1
is one of the key elements of the reading path, its performance, in particular in terms of switching time, influences in a determinant manner the access time to the memory device.
This access time consists of three principal factors:
decoding time (in a 30% proportion),
reading time (in a 40% proportion), and
switching time Tcomm of the output buffer
1
(in a 30% proportion).
At the present time, in the field of memory devices integrated on semiconductor, there is a tendency to provide devices operating with ever lower supply voltages Vcc so as to reduce the power dissipated by the device which is linked quadratically to the supply voltage Vcc. This however involves slowing propagation of the data being read.
Indeed, it is possible to determine a relationship of inverse dependence between the supply voltage Vcc and the switching time Tcomm of the output buffer
1
, whose function can be essentially assimilated with that of the logical inverter.
The switching time Tcomm is defined, for questions of symmetry, as the time necessary to take the output
6
of the buffer
1
to a voltage of Vcc/2 starting from the instant the data read is stored in a latch register. Normally, the data is read through a sense amplifier and is stored in register or latch.
To determine in a simple manner the relationship between the switching time Tcomm and the supply voltage Vcc, the pull up and pull down transistors
3
and
4
, which work in saturation zone for any supply voltage Vcc, can be considered, and the Early effect can be ignored. In this manner the transistors
3
and
4
can be considered as ideal current generators and the problem of calculating the switching time Tcomm is reduced to the charging and discharging of a constant current capacitor.
It is thus possible to find a relationship between switching time Tcomm of the device and supply voltage Vcc to solve a system consisting of the following equations:
i
=
C
·
ⅆ
V
ⅆ
t
(
1.1
)
i
=
K
·
(
W
L
)
·
(
Vgs
-
VT
)
2
(
1.2
)
where:
i is the charge and discharge current of the load capacitor Cload,
C is the value of the load capacitor Cload,
V is the voltage at the ends of the load capacitor Cload,
W/L is the form ratio of the pull-up
3
and pull-down
4
transistors,
K is Boltzmann's constant,
Vgs is the gate-source voltage of the pull-up
3
and pull-down
4
transistors, and
VT is the threshold voltage of the pull-up
3
and pull-down
4
transistors.
Integrating the equation (1.1) from 0 to Vcc/2 and substituting therein the equation (1.2) the following relationship is found:
Tcomm
=
C
·
Vcc
2
·
1
K
·
(
W
L
)
·
(
Vcc
-
VT
)
2
(
2
)
which shows the inverse dependence between the switching time Tcomm and the supply voltage Vcc.
One of the solutions conventionally proposed to obtain a certain performance in terms of switching time Tcomm for an output buffer of a memory device with the change in supply voltage Vcc calls for changing the dimensions of the transistors used and specifically their form ratio (W/L). From the relationship (2) is found:
(
W
L
)
=
C
·
Vcc
2
·
1
K
·
(
Vcc
-
VT
)
2
·
1
Tcomm
=
Vcc
(
Vcc
-
VT
)
2
α
(
3
)
For a threshold voltage VT of 1V (in reality, this threshold voltage VT changes with the change in the technological process of the device manufacturer although not departing much from the unitary value in the known processes) there are found the following relationships:
Vcc
(Vcc-VT)
2
(W/L)
(W/L)
normalized
5
16
5/16
1
3
4
3/4
12/5
2
1
2
32/5
On the basis of the results set forth in the above table there is then selected the form ratio (W/L) of the transistors to be used. A correct choice must however consider transistors with the minimum possible channel length L (and appropriate width W) so that the transistors will be protected against electrostatic charges (constraints imposed on the basis of specific safety standards).
Although advantageous in some ways this solution implies that, at low supply voltages, the surface area occupied by the final stage
2
including the pull-up
3
and pull-down
4
transistors increases considerably.
The technical problem underlying the present invention is to conceive an output stage for memory devices and having structural and functional characteristics permitting optimization of the switching time of the stage with low supply voltages for equal surface area occupied to overcome the limitations which still afflict the output stages provided in accordance with the related art.
SUMMARY OF THE INVENTION
The solution idea underlying the present invention is to improve the switching time of the output stage comprising the final pull-up/pull-down stage to increase the current flowing in the final stage while boosting the gate voltage applied to the pull-up/pull-down transistors incorporated in the final stage.
An embodiment of the invention is directed to an output stage for an electronic memory device and for low supply-voltage applications. The output stage includes a final stage of a pull-up/pull-down type made up of a pair of complimentary transistors that are insertable between a primary reference supply voltage and a second reference supply voltage. Each of the pair of complimentary transistors has a control terminal. The output stage further includes a voltage regulator having a respective output for the control terminal of each of the pair of complimentary transistors. The voltage regulator is a voltage booster using at least one bootstrap capacitor to increase a current flowing in the final stage and raising an absolute value of a voltage applied to the control terminals.
The characteristics and advantages of the output stage in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of non-limiting example with reference to the drawings.
REFERENCES:
patent: 3660684 (1972-05-01), Padgett et al.
patent: 4550264 (1985-10-01), Takahaski et al.
patent: 4570244 (1986-02-01), Sud et al.
patent: 4583203 (1986-04-01), Monk
patent: 5270588 (1993-12-01), Choi
patent: 5493245 (1996-02-01), Kao et al.
patent: 5729165 (1998-03-01), Lou et al.
patent: 1520079 (1978-08-01), None
patent: 0 647 944 (1995-04-01), None
patent: 2 246 885 (1992-02-01), None
Campardo Giovanni
Ghilardelli Andrea
Zanardi Stefano
Chang Daniel D.
Galanthay Theodore E.
Morris James H.
SGS--Thomson Microelectronics S.r.l.
Tokar Michael
LandOfFree
Output stage for a memory device and for low voltage... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Output stage for a memory device and for low voltage..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output stage for a memory device and for low voltage... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2466401