Output slew rate control

Details Output slew rate control Output slew rate control

2011-03-08

2011-03-08

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S027000, C326S030000, C326S086000, C327S112000, C327S170000

Reexamination Certificate

active

07902875

ABSTRACT:
This document discusses, among other things, output slew rate control. Methods and structures are described to provide slew rate control of an output driver circuit such as a DRAM output driver on a die. A selectable combination of series coupled transistors are configured as a parallel array of complementary inverter pairs to provide a divided voltage to a calibrator. The calibrator is configured to respond to a differential voltage to adjust the divided voltage such that the differential voltage is forced to zero. The calibrator outputs a plurality of discrete signals from an up/down counter to switch on and off the individual transistors of the parallel array to increase and decrease a collective current. In some embodiments, transistor channel currents are modulated to step-adjust a voltage based on a ratio associated with a static resistance. In various embodiments, the divided voltage is an analog voltage based on a resistance associated with trim circuitry.

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