Output reporting techniques for hard intellectual property...

Details Output reporting techniques for hard intellectual property... Output reporting techniques for hard intellectual property...

2007-07-10

2007-07-10

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S008000, C326S037000, C326S038000, C326S039000, C326S040000, C326S041000, C326S047000, C380S287000

Reexamination Certificate

active

11002577

ABSTRACT:
Techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block on an integrated circuit are provided. By reducing the frequency of the output signal, circuit blocks in the integrated circuit that operate at a lower frequency than the HIP block are able to capture the output signal. A plurality of serially coupled flip-flops store values of an HIP output signal during each period of the output signal. Logic circuitry then generates a lower frequency HIP output signal in response to the values stored in the flip-flops. Also, a flip-flop can generate a heartbeat signal that is used to determine whether a signal within an HIP block is operating properly.

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