Output interface circuits

Details Output interface circuits Output interface circuits

1981-06-17

1982-10-05

Eisenzopf, Reinhard J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

307475, 361101, H02H 320

Patent

active

043531040

ABSTRACT:
In an interface circuit having a plurality of MOS FETs and connected between an input terminal and an external circuit for converting a MOS logic level signal into a TTL level signal, there are provided a delay circuit, a capacitor impressed with a signal delayed by the delay circuit, a potential holding circuit, and a protective circuit for preventing damage to the MOS FETs in the potential holding circuit.

REFERENCES:
patent: 3796893 (1974-03-01), Hoffman et al.
patent: 3835457 (1974-09-01), Yu
patent: 4214175 (1980-07-01), Chan
Toshio Wada et al., "A 64K.times.1 Bit Dynamic ED-MOS RAM", IEEE Journal of Solid-State Circuits, vol. Sc-13, No. 5, Oct. 1978, pp. 600-606.
Toshio Wada et al., "A 15-ns 1024-Bit Fully Static MOS Ram", IEEE Journal of Solid-State Circuits, vol. Sc-13, No. 5, Oct. 1978, pp. 635-639.

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