Output FIFO data transfer control device

Details Output FIFO data transfer control device Output FIFO data transfer control device

1999-12-03

2002-08-27

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S053000, C703S014000, C712S018000, C712S225000

Reexamination Certificate

active

06442627

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output first-in first-out (or FIFO) data transfer control device for controlling transfer of arithmetic results by a geometric arithmetic core included in a geometric arithmetic processor for performing 3D graphic processing to an output FIFO and to outside the geometric arithmetic processor.
2. Description of the Prior Art
Referring now to
FIG. 21
, there is illustrated a block diagram showing the structure of a geometric arithmetic processor including a prior art output FIFO data transfer control device. In the figure, reference numeral
10
denotes a geometric arithmetic core (or geometric arithmetic engine) for performing 3D graphic processing,
20
denotes an AGP port that is an interface for connecting a host CPU (not shown) disposed outside the geometric arithmetic processor
100
with the geometric arithmetic processor
100
,
5
denotes a RC port or output control unit that is an interface to a secondary bus
6
,
30
denotes a PCI bridge between the AGP port
20
and the output control unit
5
, and
40
denotes an output FIFO (or OFIFO) data transfer control unit for controlling data transfer from each processing unit included in the geometric arithmetic core
10
to the output control unit
5
and data transfer from the output control unit
5
to the secondary bus
6
.
FIG. 22
shows a block diagram showing the structures of the prior art geometric arithmetic core
10
, the OFIFO data transfer control unit
40
, and the output control unit
5
as shown in FIG.
21
. In
FIG. 22
, reference numeral
11
denotes an integer processing unit or IPU,
111
denotes a data output register (or DRIA) for storing data on an arithmetic result from an integer ALU of the IPU
11
,
112
denotes a data output register (or DRIS) for use with a shifter used for performing integer arithmetic operations,
114
denotes a tristate buffer,
12
a
to
12
d
denote first to fourth floating-point arithmetic units (or FPU
0
to FPU
3
),
121
a
denotes a data output register (or DRFA) for storing data on an arithmetic result from a floating-point ALU of the FPU
0
12
a
,
122
a
denotes a data output register (or DRFM) for storing data on an arithmetic result from a floating-point multiplier of the FPU
0
12
a
, and
124
a
denotes a tristate buffer. Needless to say, each of the remaining floating-point processing units FPU
1
12
b
to FPU
3
12
d
includes a DRFA, a DRFM, and a tristate buffer.
Reference numeral
421
denotes a transfer mode setting section for setting a transfer mode identifying which at least one of the IPU
11
and the plurality of floating-point processing units FPU
0
12
a
to FPU
3
12
d
is to transfer data to the output control unit
5
,
431
denotes a Full flag checking section for receiving a Full flag from the output control unit
5
and for determining if the OFIFO data transfer control unit can transfer data to the output control unit
5
,
441
denotes an O-bus data input section for writing data furnished onto the O-bus
3
into an address register thereof if the data is an address, and for writing the data into a data register thereof otherwise,
451
denotes a WCR control section for controlling a word counter or WCR showing the size of each burst upon the data transfer to the output control unit
5
,
461
denotes a data output section for performing the data transfer while controlling the data transfer to the output control unit
5
,
51
denotes an output FIFO (or OFIFO) section included in the output control unit
5
, and
511
denotes an address storage section for storing a starting address of data stored in one corresponding OFIFO
512
. The output control unit
5
can include eight OFIFO sections
51
. The data output section
461
can generate and furnish a Valid flag indicating whether or not the value of the data register within the O-bus data input section
441
is valid, an address flag indicating whether or not the data temporarily stored in the O-bus data input section
441
is an address, and a final flag indicating whether or not the data is the last one of each burst, to the output control unit
5
including the eight OFIFO units
51
, as well as the data. The final flag is also a kickoff signal for triggering the output control unit
5
to transfer the data to a rendering LSI (not shown) by way of the secondary bus
6
.
Next, a description will be made as to the operation of the prior art output FIFO data transfer control device according with reference to FIG.
23
.
FIG. 23
is a timing chart showing the operation of the prior art output FIFO data transfer control device. Assume that instructions of data transfer to one OFIFO
512
are sequentially issued as follows:
(1) data transfer instruction (A); destination code ofifo
0
: from IPU to OFIFO (data
1
)
(2) data transfer instruction (B); destination code ofifo
7
: from FPU
0
, FPU
1
, and FPU
2
to OFIFO (data
2
,
3
, and
4
)
(3) data transfer instruction (C); destination code ofifo
3
: from FPU
0
and FPU
1
to OFIFO (data
5
and
6
)
(4) data transfer instruction (D); destination code ofifo
0
: from IPU to OFIFO (data
7
)
(5) data transfer instruction (E);
destination code ofifof: from FPU
0
, FPU
1
, FPU
2
, and FPU
3
to OFIFO (data
8
,
9
,
10
, and
11
)
(6) data transfer instruction (F); destination code ofifo
3
: from FPU
0
and FPU
1
to OFIFO (data
12
and
13
)
Each of the plurality of floating-point processing units FPU
0
12
a
to FPU
3
12
d
can operate according to SIMD (single instruction stream, multiple data stream) instructions and process a plurality of data when one instruction is issued. Each of the plurality of data transfer instructions (A) to (F) shown can be issued by one microcode. For example, the data transfer instruction (B) directs FPU
0
12
a
, FPU
1
12
b
, and FPU
2
12
c
to simultaneously perform arithmetic operations and to furnish arithmetic result (i.e., data
2
,
3
, and
4
) to one or more OFIFOs
512
within the output control unit
5
in the order of FPU
0
, FPU
1
, and FPU
2
.
Every time a microcode is executed and a data transfer instruction such as one of the plurality of data transfer instructions (A) to (F) as mentioned above is issued, either the IPU
11
or at least one of the plurality of floating-point processing units FPU
0
12
a
to FPU
3
12
d
associated with the data transfer instruction can furnish IPUouse or FPUouse to the OFIFO data transfer control unit
40
. As shown in
FIG. 23
, when the data transfer instruction (B) is executed and FPUouse is asserted so that FPUouse becomes state 1, and, after that, FPUouse is negated after the data transfer instruction (A) is executed first and IPUouse is asserted so that IPUouse becomes 1, and, after that, IPUouse is negated, a hold signal is asserted low. Since a plurality of data processed according to an SIMD instruction can be sent out on the signal O-bus
3
when arithmetic instructions for the same processing unit are issued sequentially as in the case that the data transfer instruction (C) is executed immediately after the execution of the data transfer instruction (B), the execution of the next data transfer instruction before reading out all data associated with the previous data transfer instruction can result in overwriting all the data stored in the corresponding data output registers, such as DRFA and DRFM of each floating-point processing unit, with new arithmetic results. To avoid the overwriting, it is necessary to assert the hold signal so as to cause the geometric arithmetic core
10
to enter the wait state in which it stops instruction pipeline processing, as shown in FIG.
23
. If the hold signal is asserted after either the IPU
11
or at least one of the plurality of floating-point processing units FPU
0
12
a
to FPU
3
12
d
associated with a data transfer instruction issued furnishes IPUouse or FPUouse to the OFIFO data transfer control unit
40
, the OFIFO data transfer control unit furnishes a read enable signal to sequentially read all data associated with the data t

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