Output ESD protection using dynamic-floating-gate arrangement

Details Output ESD protection using dynamic-floating-gate arrangement Output ESD protection using dynamic-floating-gate arrangement

1998-04-30

2000-03-07

Tokar, Michael

Electronic digital logic circuitry

Interface

Current driving

326 50, 326 86, 361 56, 361111, 257358, H03K 190175, H03K 19094, H02H 900, H02H 322

Patent

active

060345527

ABSTRACT:
A dynamic-floating-gate arrangement is used to improve the ESD robustness of driving-current-programmable CMOS output buffers in cell libraries, by suitably dynamically floating the gates of the NMOS/PMOS buffers using a small-dimension CMOS device having its drain connected to the gate of an unused CMOS buffer, its source connected to one of two voltage sources, and its gate connected between a resistance, that is connected between the two voltage sources, and a capacitance connected between the resistance and the same one of the two voltage sources as the source of the small-dimension CMOS device.

REFERENCES:
patent: 5345356 (1994-09-01), Pianka
patent: 5345357 (1994-09-01), Pianka
patent: 5631793 (1997-05-01), Ker et al.
patent: 5745323 (1998-04-01), English et al.
patent: 5781388 (1998-07-01), Quigley
patent: 5877930 (1999-03-01), Gist

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