Output ESD protection circuit

Details Output ESD protection circuit Output ESD protection circuit

1992-09-16

1993-06-08

Munson, Gene M.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257363, H01L 2906, H01L 2978

Patent

active

052182223

ABSTRACT:
The basic component of the output ESD protection circuit of the present invention comprises a low resistance connected in series between an output pad and conventional active output pad pullup and pulldown drivers. In a preferred embodiment, a polysilicon resistor is connected in series between an output pad and a metal bus. On the metal bus, a lateral bipolar device is connected in parallel to an n-channel pulldown at an output node and a common potential (conventionally labeled as V.sub.SS). The pullup device is also an active n-channel pullup device connected between an operating potential (conventionally labeled as V.sub.CC) and the output node. Both drains of the two n-channel devices have n-well underneath the n+ diffusion in the area where metal contacts are formed to thereby prevent metal spiking to the substrate during an ESD event. This circuitry combination provides ESD protection equal to or greater than the voltage range of +8000/-2000 V for the HBM response (the Mil. Std. human body model [HBM] test model) as well as protection equal to or greater than the voltage range of +900/-700 V for the MM EIAJ response (the EIAJ machine model [MM] test model). The concept of using a low resistance between a pad and associated active devices (i.e., ESD protection circuitry) will work in combination with other ESD protection circuitry layouts and work equally well for input pad ESD protection.

REFERENCES:
patent: 4733285 (1988-03-01), Ishioka et al.
patent: 4819047 (1989-04-01), Gilfeather et al.
patent: 5072271 (1991-12-01), Shimizu et al.
patent: 5181092 (1993-01-01), Atsumi
"Output ESD Protection Techniques for Advanced CMOS Proceedings" Duvvury, et al., 1988 EOS/ESD Symposium Proceedings, pp. 206-211.
"ESD Phenomena and Protection in CMOS Output Buffers" Duvvury, et al., 1987 IEEE/IRPS, pp. 174-180.
"Improving the ESD Failure Threshold of Silicided nMOS Output Transistors by Ensuring Uniform Current Flow", Polgreen et al., 1989 EOS/ESD Symposium Proceedings, pp. 167-174.

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