Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2001-09-07
2003-09-16
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S032000, C327S378000
Reexamination Certificate
active
06621303
ABSTRACT:
The present application claims priority under 35 U.S.C. §119 to Korean Application No. 2000-55203 filed on Sep. 20, 2000, which is hereby incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to an output driver that lowers power consumption and reduces layout area.
2. Description of the Related Art
A semiconductor integrated circuit, for example, a Rambus-DRAM, uses an open-drain method for transmitting data generated by the integrated circuit to an output pad. The open-drain method is one of numerous data transmitting methods, and includes as shown in
FIG. 1
a structure in which a pull down transistor
6
is connected to an output pad (PAD). When data generated inside of a chip is transmitted to the PAD in response to enable signals (EN), if an output of an inverter
4
is a logic high level, the pull down transistor
6
turns on, and the voltage level at the PAD becomes a logic low VOL (Vterm-I
OL
×Rterm) level. If the output of the inverter
4
is logic low, the pull down transistor
6
turns off, and the voltage level at the PAD becomes VOH by an external voltage (Vterm) through a resistance (Rterm) connected to the PAD outside the chip. Thus, the PAD becomes logic high. Therefore, the PAD becomes logic high identical to the data inside the chip. The open-drain method can also be realized by a method of connecting a pull up transistor, instead of the pull down transistor
6
connected to the PAD of FIG.
1
. Incidentally, the data generated inside the chip and the enable signal EN are input to a logical NAND gate, which provides an output therefrom to inverter
4
.
In
FIG. 1
, the inverter
4
plays the role of a pre-driver which transmits the data generated by the chip to the pull down transistor
6
, and thus operates the pull down transistor
6
. Here, the inverter
4
and the pull down transistor
6
become an output driver
10
. Particularly, the inverter
4
directly operates the pull down transistor
6
, and the operating capability of inverter
4
thus determines how fast the pull down transistor
6
turns on to enable the voltage level at the PAD to become VOL, that is a logic low level. The operating capability of the inverter
4
is determined not only by the size and the width/length of the inverter
4
itself, but also by changes to the threshold voltage, the operating voltage, and temperature according to a semiconductor manufacturing process.
For example, the operating capability of the transistors, which form the inverter
4
as having a raised threshold voltage or a lowered voltage, can be lowered. It would then take a long time to swing a gate voltage level of the pull down output transistor to logic high, so that the switching speed of the pull down transistor becomes slower. As a result, the operating speed of a semiconductor memory device having an open-drain output terminal of
FIG. 1
becomes slower. To solve this problem, an output driver such as that shown in
FIG. 2
is used.
The output driver
200
of
FIG. 2
includes a first data selector
210
, a second data selector
220
, a first output driver enabler
230
, a second output driver enabler
240
, a first operator
250
, and a second operator
260
. The first data selector
210
operates in accordance with clock signals (CLK, CLKB) and the second data selector
220
operates in accordance with delay clock signals (CLK_DLY, CLKB_DLY), and the first and second data selectors
210
and
220
select the data generated by the chip, that is, even-numbered data or odd-numbered data. The delay clock signals (CLK_DLY, CLKB_DLY) are generated respectively by clock delays
270
and
280
based on control signals (S
1
, S
2
), by sensing changes in a semiconductor manufacturing process, voltage and temperature. In the first and second operators
250
,
260
, the gate voltage level of output transistors
251
,
261
is sufficiently high, in response to complex control signals (S
1
, S
2
), to induce a fast switching of the output transistors
251
,
261
.
However, since in this output driver
200
, clock signal lines are connected to clock delays
270
and
280
that generate delay clock signals (CLK_DLY, CLKB_DLY), a line load on clock signals (CLK, CLKB) appears large. If the operating frequency is high, the line load causes a problem by consuming too much power. In addition, because two data selectors
210
,
220
are necessary, layout area becomes large. Therefore, an output driver having lower power consumption and reduced layout area is required.
SUMMARY OF THE INVENTION
The present invention is therefore directed to an output driver having reduced power consumption and layout area, which substantially overcomes one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is an object of the present invention to provide an output driver capable of lowering power consumption and reducing layout area.
Accordingly, to achieve the above and other objects, there is provided an output driver controlled by control signals and which transmits internally generated data to pads, and which senses changes in process, voltage, and temperature, in response to clock signals, including: a data selector that selects the internally generated data in response to clock signals, an output driver enabler that outputs data selected by the data selector in response to output driver enable signals, a first driver that transmits the output of the output driver enabler to pads, a data delay that delays the output of the output driver enabler for a predetermined time in response to control signals, and a second driver that transmits the output of the data delay to pads.
The data selector may be configured to select even-numbered data from the internally generated data in response to clock signals, and to select odd-numbered data from the internally generated data in response to inverted signals of the clock signals.
According to a preferred embodiment, the data delay includes: a first inverter chain, in which a plurality of inverters are connected in series between an output of the output driver enabler and an input of the second driver, and a second inverter chain, in which a plurality of inverters, activated in response to control signals between a middle node of the inverter chain and an input of the second driver, are connected in series.
According to another preferred embodiment, the data delay includes: a first inverter chain, in which a plurality of inverters between an output of the output driver enabler and an input of the second driver are connected in series, and a second inverter chain, in which a plurality of inverters, activated in response to control signals between an output of the output driver enabler and an input of the second driver, are connected in series. A middle node of the first inverter chain and a middle node of the second inverter chain are connected to each other.
According to the output driver of the present invention, the layout area can be reduced by removing the conventional data selector, and power consumption can be lowered by reducing the line load of the clock signals, because the delay clock signals need not be generated from the clock signals.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 5331220 (1994-07-01), Pierce et al.
patent: 5489858 (1996-02-01), Pierce et al.
Chang Daniel
Volentine & Francos, PLLC
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