Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-09-02
2001-09-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S083000
Reexamination Certificate
active
06285215
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to output circuits and, more particularly, to output drivers having the ability to control the rise and fall times of the signals output therefrom.
2. Description of the Background
Drive circuits, or drivers as they are commonly called, are used in a variety of applications. Typically, the driver acts as an interface between a logic circuit, or other circuitry where signals are being manipulated at very low levels and circuits or loads which require high signal levels or large current levels. For example, drivers are found in various types of memory devices as the interface between data pads and the internals of the memory device. In such an environment, the driver is typically used to drive the data pad to a first voltage to represent a logic level 1 and a second voltage to represent a logic level 0. The driver typically must source sufficient current to enable signals available at the data pads to travel significant lengths along buses or to be sensed by other types of loads.
Prior art drive circuits typically utilize a pair of output drive transistors designed to operate in a complementary fashion. For example, the data pad may be connected to the first voltage through an N-type transistor and connected to the second voltage through a P-type transistor. When one of the transistors is on, the other transistor is off. In modern circuits, both transistors may be off to allow the data pad to receive data.
When designing drivers, it is necessary to insure that the transistors turn off as quickly as possible so that the situation does not exist wherein both transistors are on. Additionally, because of the high operating speeds of integrated circuits, it is necessary for the transistors to rapidly change state. It is also desirable to produce a driver which provides an output signal that is substantially symmetrical with respect to its leading edge and falling edge. However, due to process variations, the signal path servicing the N-type transistor may differ from the signal path servicing the P-type transistor such that the resulting output signal is not symmetric. Additionally, timing specifications for various applications may require adjustment of the leading or falling edge of the output signal. Accordingly, the need exists for a driver capable of compensating for process variations and for providing flexibility with respect to the timing of the output signal produced by the driver.
SUMMARY OF THE PRESENT INVENTION
The present invention is directed to a programmable output driver comprising a first signal path for pulling an output node up to a first voltage level and a second signal path for pulling the output node down to a second voltage level. A plurality of capacitors and a plurality of switches arc provided for programmably connecting certain of the plurality of capacitors to the second signal path to control the falling edge of a signal output from the driver. In a preferred embodiment, the first signal path includes a boot circuit which primarily controls the leading edge of the signal output from the driver.
The present invention is also directed to a method of operating an output driver comprising driving an output node of the driver to a first voltage level in response to the driver receiving a first input signal at a first signal path and driving the voltage available at the output node of the driver to a second voltage level in response to the driver receiving a second input signal at a second signal path. The capacitive load of the second path is programmably controlled to control the rate of change at the output node from the first voltage level to the second voltage level.
Because the apparatus and method of the present invention provide the ability to control the capacitive load presented by the second signal path, the capacitive load of the second signal path may be balanced with the capacitive load of the first signal path so that the rise and fall times of a signal output from the drive circuit are equal. However, because the falling edge of the signal output from the driver can be controlled, the overall timing of the output signal can be controlled so that different timing specifications can be met. The ability to programmably control at least one of the edges of the output signal also provides the ability to compensate for process variations. Those advantages and benefits, and others, will be apparent from the Description of the Preferred Embodiment hereinbelow.
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Le Don Phu
Micro)n Technology, Inc.
Thorp Reed & Armstrong LLP
Tokar Michael
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