Output driver circuit using thin and thick gate oxides

Details Output driver circuit using thin and thick gate oxides Output driver circuit using thin and thick gate oxides

2000-06-16

2002-08-06

Le, Don Phu (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S058000, C326S081000

Reexamination Certificate

active

06429686

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to an input/output structure for an integrated circuit and, in particular, to an output driver using thin and thick gate oxides.
BACKGROUND OF THE INVENTION
As integrated circuit (IC) designs become more complex, IC developers are moving toward smaller geometries to provide these designs without sacrificing valuable board space. However, smaller geometries require lower power supply voltages due to transistor breakdown. Specifically, for a given power supply voltage, the electric field strength, i.e. the change in voltage per unit length, that a transistor is exposed to increases as the size of the transistor is reduced.
The maximum electric field tolerance can be a limiting factor on the minimum transistor size. For example, a typical maximum gate oxide field strength for silicon dioxide gates is about 3 megavolts per centimeter. High electric fields inside a transistor can reduce the mean time to failure, and can destroy transistors when an electric field exceeds the breakdown value for a given material in a transistor, such as the gate oxide in CMOS devices. Therefore, in 0.35 &mgr;m CMOS technology, a typical power supply of 3.3 Volts (a maximum power supply of 3.3 Volts+10%) is provided, whereas in 0.25 &mgr;m CMOS technology, a typical power supply of 2.5 Volts (a maximum power supply of 2.5 Volts+10%) is provided.
An IC typically has a plurality of input/output (I/O) circuits that act as an interface between the internal circuits of the IC and the environment external to the IC.
FIG. 1
illustrates a typical I/O circuit
100
that includes an input driver
101
and an output driver
103
. Output driver
103
drives an electrical signal generated by one or more internal circuits that provide a function f to a pad
104
that is connected to the external environment. Input driver receives a signal from the external environment through pad
104
and drives that signal to one or more internal circuits
102
.
When two ICs having different power supply levels are coupled together, the I/O circuit is generally required to prevent damage to transistors in the device having the lower power supply level. For example, in one illustrative technology, the XC9500XL™ complex programmable logic device (CPLD), available from Xilinx, Inc., has 5 Volt tolerant I/O pins that accept 5 Volt, 3.3 Volt, and 2.5 Volt signals.
To further complicate IC design, some IC structures are exposed to different voltages on chip. For example, the XC9500XL CPLD includes an on-chip charge pump that generates high voltages of, in one embodiment, +8 Volts or −8 Volts. Transistors that transfer such high voltages require corresponding thick gate oxides to prevent transistor breakdown. However, the flash memory cells of the XC9500XL CPLD are programmed/erased by these high voltages. Therefore, these memory cells require an intermediate gate oxide thickness. Finally, standard logic in the XC9500XL CPLD is not exposed to the high voltages of the charge pump and thus transistors that comprise the standard logic require only a thin gate oxide.
The thicknesses vary depending on the technology. For example, in the XC9500XL CPLD implemented in 0.35 &mgr;m technology, devices have gate oxide thicknesses of 150 Angstroms, 100 Angstroms and 70 Angstroms. The 150 Angstrom thickness is used for transistors transferring the large voltages generated by the charge pump. The 100 Angstrom thickness is used for the tunneling oxide of the memory cells, i.e., between the floating gate and the substrate. (Note that the thickness of the oxide between the control gate of such a memory cell and the floating gate is typically 150 Angstroms). Finally, the 70 Angstrom thickness is used for the transistors comprising the standard logic, including the I/O circuitry.
Because of its interface to external circuits, the I/O circuitry is of particular concern to IC designers. Specifically, output drivers should provide a fast I/O delay when driving a predetermined capacitive load while protecting all transistors in the output driver from high voltages on the I/O pad.
FIG. 2
illustrates a prior art, output driver
200
in a XC9500XL CPLD. Output driver
200
includes a pull-up transistor
205
coupled between an I/O voltage supply Vddio and an I/O pad
211
. Output driver
200
further includes a pull-down transistor
209
and an isolation transistor
210
coupled in series between a ground voltage and pad
211
. Isolation transistor
210
has its gate coupled to an internal supply voltage Vddint and therefore is conducting. In one embodiment, voltage Vddint is 3.3V.
In an enable (output) mode, either pull-up transistor
205
or pull-down transistor
209
is on, thereby providing the appropriate output data DOUT signal to pad
211
. In contrast, in a tristate mode, both transistors
205
and
209
are off, thereby allowing pad
211
to provide an input signal to an input driver (not shown) and thereafter to the internal circuits (also not shown) of the PLD.
Input drivers are well known in the art and therefore are not described in detail herein. The internal circuits of the XC9500XL device are described in detail on pages 5-5 to 5-15 of “The 1999 Programmable Logic Data Book”, published by Xilinx, Inc. and incorporated by reference herein.
Output driver
200
receives an output enable signal OE that determines whether output driver
200
is tristated or active. In the tristate mode, when the output enable signal OE is low, then an inverter
201
provides a high signal to an input terminal of a NOR gate
202
, thereby ensuring that NOR gate
202
outputs a low signal. An inverter
203
inverts this low signal. A protection transistor
204
has the I/O voltage Vddio applied to its gate. Voltage Vddio turns on protection transistor
204
, thereby transferring the high signal output from inverter
203
(less one threshold voltage of its associated NMOS transistor) to the gate of pull-up transistor
205
and turning off that transistor. Note that the power supply provided to the logic of output driver
200
, unless otherwise noted, is voltage Vddint.
Also in the tristate mode, the low OE signal is provided to an input terminal of NAND gate
207
, thereby ensuring that NAND gate
207
outputs a high signal. An inverter
208
inverts that high signal and therefore provides a low signal to the gate of pull-down transistor
209
. In this manner, transistor
209
is also turned off.
In the active mode, a high OE signal results in a low signal provided to NOR gate
202
and a high signal provided to NAND gate
207
. Therefore, the output signals of those gates depend on the state of the data output DOUT signal. If DOUT is high, then both NOR gate
202
and NAND gate
207
output a low signal. In this manner, transistor
205
is turned off, but transistor
209
is turned on, thereby providing a low signal on pad
211
. Thus, driver
200
provides an inverted DOUT signal on pad
211
during the active mode.
On the other hand, if DOUT is low, then both NOR gate
202
and NAND gate
207
outputs a high signal. In this manner, transistor
209
is turned off, but transistor
205
is turned on, thereby providing a high signal on pad
211
.
Pull-down transistor
209
must be protected when pad
211
is used as an input pin and carries a voltage up to 5.5V. Isolation transistor
210
has its gate connected to Vddint (3.3 Volts) and thus the voltage at the drain of pull-down transistor
209
is no more than Vddint minus an NMOS threshold drop (i.e., 3.6−0.7=2.9). Therefore, transistor
209
, which can withstand a junction (gate to source or gate to drain) voltage of 3.6 Volts, will not experience damaging voltage levels.
Pull-up transistor
205
must be prevented from conducting current to Vddio (3.3 Volts or 2.5 Volts) when pad
211
is used as an input pin and carries a voltage up to 5.5V. Thus, output driver
200
includes a well driver
206
that maintains a sufficiently high voltage to the well and the gate of pull-up transistor
205
to prevent leakage current through

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