Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2000-01-25
2002-06-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C326S090000, C326S083000, C327S108000, C327S109000, C327S170000
Reexamination Certificate
active
06400177
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to output drivers, and in particular to output drivers that must meet specified output impedance and current characteristics.
BACKGROUND ART
Output drivers are well known in the electronic arts. An output driver typically comprises a “pull-up” transistor that is on when the output signal needs to transition from a low to high value and a “pull-down” transistor that is on when the output signal needs to transition from high to low.
FIG. 1
illustrates a typical CMOS output driver
10
. Pad
12
is the point of signal output. The term “pad” as used herein simply means the point of signal output and does not have any other more limited meaning. Typically, in an application involving a system bus, e.g. a Universal Serial Bus, the output will be to a cable such as cable
13
. A typical cable will present a capacitive load to a signal output at pad
12
. Such a load is represented by capacitor
14
which has a capacitance C
1
. When the signal voltage value at input
11
is high, the voltage value at gate G
1
-
1
of pull-up transistor Ni-i is high, and, due to inverter
15
, the voltage value at gate G
2
-
1
of pull-down transistor N
2
-
1
is low. As a result, transistor N
1
-
1
is on, transistor N
2
-
1
is off, and pull-up current ILH flows as shown, charging up capacitive load
14
and driving the voltage at pad
12
to a high value. Conversely, when the signal voltage value at input
11
is low, transistor N
1
-
1
is off and pull-down transistor N
2
-
1
is on. As a result, pull-down current IHL flows draining the charge on the cable and bringing the voltage at pad
12
down to a low level.
In some applications, it is desirable for output drivers to meet particular output impedance and signal transition time characteristics. For example, Revision 1 of the Universal Serial Bus Specification sets forth particular driver requirements. In particular, the output impedance must be between 3 ohms and 15 ohms. Furthermore, the signal transition times (rise time and fall time) must be between 4-20 ns and the high signal voltage must be between 2.8 v-3.6 v. Assuming constant capacitance, and because I=Cdv/dt, the signal transition time and signal voltage requirements effectively set a current requirement. For example, assuming a high voltage of 3.2 v and a transition time of 12 ns (both values in the middle of the USB required range) and assuming C=50 pF, ILH=IHL=50 PF(3.2 v/12 ns)=13.3 mA. However, given the characteristic voltage/current relationship of a CMOS transistor, delivering a desired output current during signal transitions can be difficult.
FIG. 2
shows an example of the possible approximate shapes of the voltage/current curves for a typical NMOS transistor, such as pull-down transistor N
2
-
1
in the output driver
10
of FIG.
1
. These curves help illustrate the difficulty of meeting particular output current and impedance requirements. Pull-down transistor N
2
-
1
has three terminals: drain D
2
-
1
, source S
2
-
1
, and gate G
2
-
1
.
FIG. 2
shows
3
curves. Each curve illustrates the relationship between the drain-to-source voltage VDS and the drain-to-source current IDS for a given gate-to-source voltage VGS.
In a typical driver circuit, the gate-to-source voltage VGS would be substantially constant at, for example, VGS
1
. In output driver
10
, the pad output voltage at pad
12
is the same as the drain-to-source voltage VDS of the pull-down transistor N
2
-
1
. If the ideal output current is IHL=IDS=IDS
1
, then VGS will typically be set at VGS=VGS
1
. As illustrated along the VGS
1
curve in
FIG. 2
, the impedance Z=V/I is steadily decreasing as VDS drops toward VDS
1
. However, once VDS drops below VDS
1
, the impedance is not decreasing rapidly enough to maintain the current level, and IDS begins to drop below IDS
1
. For example, when VDS has dropped to VDS
2
, IDS=IDS
2
.
For some applications, such as an output driver for use under the USB specification requirement, the output impedance of a driver such as driver
10
will be too high in the regions of low drain-to-source voltage. Thus IDS will drop too low during the signal transition and the signal transition time may be too slow. If the gate-to-source voltage were set at a higher value, such as VGS
2
, the impedance when VDS=VDS
2
would be relatively lower and a higher transition current IDS=IDS
1
would be maintained even as the output voltage VDS dropped. However, in a driver such as driver
10
in
FIG. 1
, VGS cannot be set at VGS
2
during the entire transition because when VDS is greater than VDS
2
, the output transition current will be too high, and USB or other specification requirements might not be met.
FIG. 3
illustrates an earlier driver
30
known in the art for attempting to deal with the problem of maintaining steady current flow during signal transitions. During the low to high transition, pull-up transistors P
1
-
3
and P
2
-
3
turn on at different times. When an input signal first transitions from low to high, P
1
-
3
turns on and pull-up current ILH
1
begins to flow, driving up the voltage at pad
32
(pad
32
is attached to cable
33
which is a capacitive load as represented by capacitor
34
having a capacitance C
2
). As the output voltage at pad
32
increases, the source-to-drain voltage of transistor P
1
-
3
decreases, and eventually pull-up current ILH
1
begins to decrease. However, after a delay due to delay circuit D
1
-
3
, transistor P
2
-
3
turns on and pull-up current ILH
2
begins to flow, and the overall output pull-up current becomes ILH
1
+ILH
2
. Conversely, during the high to low transition, pull-down transistors N
1
-
3
and N
2
-
3
are turned on at different times. When an input signal at input
31
first transitions from high to low, pull-down transistor N
1
-
3
turns on and pull-down current IHL
1
begins to flow. However, as the voltage at pad
32
decreases, the drain-to-source voltage of transistor N
1
-
3
also begins to drop and eventually, pull-down current IHL
1
begins to decrease. After a delay caused by delay circuit D
2
-
3
, pull-down transistor N
2
-
3
is turned on and output current IHL
2
begins to flow. Thus the overall pull-down current becomes IHL
1
+IHL
2
.
This staggering of two pull-up and two pull-down transistors should, in theory, allow relatively steady pull-up and pull-down currents to be maintained during signal transitions. However, implementing delay circuits that deliver the proper amount of delay to obtain desirable results is difficult. Variations in operating parameters cause variations in the delay implemented by delay circuits D
1
-
3
and D
2
-
3
. If the delay is too short, then the output impedance is too low at the beginning of a signal transition and the output current will be too high. If the delay is too long, the output impedance will remain too high as the as the signal transition progresses, and the transition output current will be too low, or possibly even drop to zero.
SUMMARY OF THE INVENTION
A present embodiment of the invention provides one or more voltage response circuits that modify a voltage difference between a first terminal and a second terminal of a pull-up or pull-down transistor in response to a change in a voltage difference between a third terminal and the second terminal of the pull-up or pull-down transistor. As a result, the transistor's impedance and current flow may be adjusted to better meet the requirements of particular applications.
REFERENCES:
patent: 5184033 (1993-02-01), Chiao et al.
patent: 5287022 (1994-02-01), Wilsher
patent: 5479124 (1995-12-01), Pun et al.
patent: 5808481 (1998-09-01), Thompson
patent: 5854560 (1998-12-01), Chow
patent: 5973512 (1999-10-01), Baker
patent: 6114895 (2000-09-01), Stephens
patent: 6201412 (2001-03-01), Iwata et al.
patent: 6281706 (2001-08-01), Wert et al.
Matsushita Electric Industrial Co.
Morrison & Foerster / LLP
Tan Vibol
Tokar Michael
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