Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2006-10-24
2006-10-24
Barnie, Rexford (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S095000, C326S097000, C326S112000, C365S185040
Reexamination Certificate
active
07126379
ABSTRACT:
An output device for static random access memory is disclosed, which has a precharger, a charge and discharge path circuit, a voltage hold circuit and an output inverter. The precharger connects to a common output node of a plurality of memory cells. When one of the memory cells is to be read, the common output node is precharged to a high potential. The charge and discharge path circuit connects to the common output node and controls an output voltage on its output node in accordance with an internal first grounding path on or not. The voltage hold circuit connects to both the output node of the path circuit and the common output node and controls a voltage of the common output node in accordance with both the output voltage of the path circuit and an internal second grounding path. When the precharger is precharging, the second grounding path is disconnected.
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Bacon & Thomas PLLC
Barnie Rexford
VIA Technologies Inc.
White Dylan
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