Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2001-09-07
2003-01-07
Chang, Daniel D. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S027000, C326S083000, C327S109000
Reexamination Certificate
active
06504397
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to CMOS signaling and transmit drivers and specifically to devices and methods for terminating such drivers.
BACKGROUND ART
Typically, transmit drivers used in CMOS signaling applications utilize discreet off-chip resistors for output termination. Off-chip components add additional system costs and are generally outside the control of the chip fabricator which may result in system performance degradation. Generally, off-chip termination results in unterminated circuit portions composed of package parasitics and internal circuitry. These unterminated circuit portions can cause large reflections on the signal line.
Prior art devices and methods having integrated open drain output drivers, and internal fixed or external fixed termination resistors are limited, providing only fixed output voltage swing and fixed common mode voltage levels. Moreover, the output current of the integrated open drain driver flows through a bond wire and package inductance to create a voltage signal across the external termination resistors. The voltage drop across these inductances causes problems at higher switching speeds. Prior art systems and methods do not provide sufficient electrical control of the output driver's source impedance.
Therefore, it would be advantageous to build termination resistors on the chip rather than using discreet off-chip resistors. However, CMOS application processes do not provide a material from which accurate and temperature insensitive resistors may be produced. Moreover, DC-coupled systems require a controlled common mode voltage level at the output of the line driver. For applications where the line length and therefore the line attenuation is not known, it furthermore would be desirable to be able to change the output amplitude of the transmitted signal after the chip is embedded in the application.
Therefore, there is a need for a new and improved line driver device and method for providing precise on-chip termination resistors to improve system performance, versatility, and reduce costs. Such a new and improved line driver device should be able to accurately set the value of the internal output termination resistors, the value of the output common mode voltage, and the value of the output signal amplitude independently of each other. Furthermore, the line driver device should maintain these three parameters independently from manufacturing process tolerances, temperature and supply voltage variations. The present invention provides solutions for these and other problems not addressed by the prior art.
BRIEF SUMMARY
The present invention provides a device and method for providing onchip termination resistors for high speed CMOS signaling and transmit line drivers. Furthermore, the present invention provides a fully integrated differential line driver with an independent control over the internal output termination resistor, the value of the output common mode voltage level, and the value of the output signal amplitude. Advantageously, the internal output termination resistor, the output common mode voltage level, and the value of the output signal amplitude are automatically calibrated based on a precise electrical reference.
Thus, the present invention has many advantages and benefits over the prior art. For example, the present invention may offer a cost savings by eliminating the need for external termination components. Additionally, the present invention may provide superior electrical source impedance termination of the transmit line driver. That is, the system and method of the present invention terminate the output of the line driver, creating a system which is insensitive to manufacturing process tolerances, temperature and supply variations. Moreover, since the present system and method terminate the driver inside the chip, at the output of the line driver, signal reflections on the signal line are kept to a minimum. Beneficially, post manufacturing calibration of the output voltage swing, output common mode voltage level, and output termination resistor value may be performed independently.
Thus, the present invention may be utilized in, but is not limited to, integrated line drivers, integrated output buffers, high speed digital signaling and serial links.
Further objects, features and advantages of the invention will become apparent from consideration of the following description and the appended claims when taken in connection with the accompanying drawings.
REFERENCES:
patent: 5581197 (1996-12-01), Motley et al.
patent: 6054874 (2000-04-01), Sculley et al.
IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000 Entitled: Low-Power Area-Efficient High-Speed I/O Circuit Techniques—pp. 1591-1595 By: Ming-Ju Edward Lee, william J. Dally, Member, IEEE, and Patrick Chiang.
Hart Siegfried
Setty Palaksha
Brinks Hofer Gilson & Lione
Chang Daniel D.
Infineon Technologies North America Corp.
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