Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-08-16
2009-11-03
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S028000
Reexamination Certificate
active
07612579
ABSTRACT:
An output circuit includes a counter circuit that generates an ODT control signal ODTa, plural driver circuits having the ODT function, a synchronizing circuit that synchronizes a signal transmitted from the counter circuit to the driver circuit with an internal clock DLL, a first selecting circuit that activates one of plural ODT selection signals ODTb and ODTc based on the ODT control signal ODTa, and a second selecting circuit that selects a driver circuit to be used out of the plural driver circuits based on the activated ODT selection signal. The first selecting circuit is provided between the counter circuit and the synchronizing circuit, and the second selecting circuit is provided between the synchronizing circuit and the driver circuit.
REFERENCES:
patent: 2004/0090239 (2004-05-01), Ikeoku et al.
patent: 2006/0158214 (2006-07-01), Janzen et al.
patent: 2006/0158216 (2006-07-01), Aoyama et al.
patent: 2003-133943 (2003-05-01), None
Cho James H.
Elpida Memory Inc.
Foley & Lardner LLP
Tran Jany
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