Output circuit of a memory and method thereof

Details Output circuit of a memory and method thereof Output circuit of a memory and method thereof

2007-12-25

2007-12-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S207000

Reexamination Certificate

active

11385535

ABSTRACT:
An output circuit of a memory is provided. The output circuit includes a first pre-charge circuit, coupled to a read bit line which is coupled to a plurality of memory cells, pre-charging the voltage of the read bit line to a logic high level before a stored bit of a target memory cell is read to the read bit line, wherein the target memory cell is one of the plurality of memory cells, and a sense amplifier, coupled to the read bit line, detecting the voltage of the read bit line after the stored bit of the target memory cell is read to the read bit line, and comparing the voltage of the read bit line with the logic high level to respectively generate a comparison result signal and an inverse comparison result signal to a first output node and a second output node.

REFERENCES:
patent: 6046942 (2000-04-01), Hwang et al.
patent: 6181634 (2001-01-01), Okita
patent: 6222777 (2001-04-01), Khieu
patent: 6317379 (2001-11-01), Argyres
patent: 6665215 (2003-12-01), Thomas et al.
patent: 2005/0180197 (2005-08-01), Huang
patent: 2000215674 (2000-08-01), None
patent: 1226638 (2005-01-01), None
patent: 1240277 (2005-09-01), None
TW Office Action mailed Jul. 23, 2007.

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