Output circuit for electronic devices

Details Output circuit for electronic devices Output circuit for electronic devices

2000-04-11

2001-12-11

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S057000, C326S083000

Reexamination Certificate

active

06329842

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to an output circuit, and more particularly, to an output circuit for preventing leakage current from flowing through the output circuit when a voltage higher than the power supply level is applied to the output terminal.
FIG.
1
(
a
) is a schematic circuit diagram showing a first example of an output circuit
50
used in an electronic device. The output circuit
50
includes a push-pull circuit having a CMOS configuration. The source of a push PMOS transistor Q
51
is connected to a power supply Vdd, and the source of a pull NMOS transistor Q
52
is connected to the ground GND. An internal circuit (not shown) provides the gate of the PMOS transistor Q
51
(i.e., internal input terminal P
51
) with a first internal signal in
51
and the gate of the NMOS transistor Q
52
(i.e., internal input terminal P
52
) with a second internal signal in
52
. The drains of the MOS transistor Q
51
, Q
52
are connected to each other. A node between the drains (i.e., output terminal P
53
of the output circuit
50
) is connected to a bus line (not shown).
During normal output operation of the output circuit
50
, the output circuit
50
receives the first and second internal signals in
51
, in
52
, the logic levels of which are the same, from the internal circuit. The output circuit
50
then provides a signal, the logic level of which is inverted from the levels of the first and second internal signals in
51
, in
52
, as an output data out
1
to the bus line via the output terminal P
53
. That is, in response to the first and second internal signals in
51
, in
52
, the output circuit
50
provides the bus line with output data signals out
1
having the power supply level Vdd and the ground level GND. When the first internal signal in
51
provided to the MOS transistors Q
51
goes high and the second internal signal in
52
provided to the transistor Q
52
goes low, the MOS transistors Q
51
, Q
52
are deactivated and the output terminal P
53
is set to a high impedance (Hi-Z) state.
FIG. 2
is a schematic diagram showing a second prior art example of an output circuit
60
employed in an electronic device. The output circuit
60
includes a push-pull circuit formed by connecting NMOS transistors Q
61
, Q
62
in series between a power supply Vdd and the ground GND. An internal circuit (not shown) provides the gate of the NMOS transistor Q
61
(i.e., internal input terminal P
61
) with a first internal signal in
61
and the gate of the NMOS transistor Q
62
(i.e., internal input terminal P
62
) with a second internal signal in
62
. A node between the NMOS transistors Q
61
, Q
62
(i.e., output terminal P
63
of the output circuit
60
) is connected to a bus line.
During normal output operation of the output circuit
60
, the output circuit
60
receives the first and second internal signals in
61
, in
62
, the logic levels of which are inverted from each other. The output circuit
60
then provides the bus line with an output data signal out
2
having the same logic level as the first internal signal in
61
. When the internal signals in
61
, in
62
provided to the output circuit
60
both go low, the MOS transistors Q
61
, Q
62
are deactivated and the output terminal P
63
is set to a high impedance (Hi-Z) state.
However, data having a level higher than the power supply levels of the output circuits
50
,
60
may be provided to the bus line from other devices. In such case, the application of a voltage, which level is higher than the power supply, to the corresponding output terminals P
53
, P
63
would result in the shortcomings discussed below.
In the output circuit
50
, the application of a voltage higher than the sum of the power supply Vdd voltage and a forward voltage VDF between the drain and back gate of the transistor Q
51
(Vdd+VDF) to the output terminal P
53
would cause a leakage current to flow through the output terminal P
53
, the source and back gate of the PMOS transistor Q
51
, and to the power supply Vdd, as shown by the broken line in FIGS.
1
(
a
) and
1
(
b
). This is because the circuit between the source and the back gate of the PMOS transistor Q
51
is equivalent to a diode connected in a forward direction.
Further, the transistor Q
51
is deactivated when a voltage higher than the sum of the gate voltage of the PMOS transistor Q
51
and a threshold voltage Vthp of the transistor Q
51
is applied to the output terminal P
53
in a high impedance (Hi-Z) state. This would cause a leakage current to flow from the bus line and to the power supply Vdd through the output terminal P
53
and the drain and source of the PMOS transistor Q
51
, as shown by the broken line in FIGS.
1
(
c
) and
1
(
d
).
In the output circuit
60
, leakage current does not flow when the voltage of the data signal at the bus line is higher than the power supply Vdd voltage. This is because the circuit between the drain (output terminal P
63
) and the back gate of the NMOS transistor Q
61
is equivalent to a diode connected in a reverse direction. However, the output circuit
60
outputs the data signal out
2
having a voltage lower than the gate voltage of the transistor Q
61
by the threshold voltage Vthn of the NMOS transistor Q
61
. Accordingly, the data signal generated by the output circuit
60
cannot perform full swing between the power supply Vdd level and the ground GND level.
When a voltage higher than the power supply Vdd level is applied to each of the output terminals P
53
, P
63
, the potential difference between the output terminals P
53
, P
63
and the associated input terminals P
51
, P
52
, P
61
, P
62
is increased. Thus, a gate oxidation film, which is applied to each of the MOS transistors Q
51
, Q
52
, Q
61
, Q
62
between the source and gate (FIGS.
1
(
b
) and
1
(
d
)), is formed with increased thickness to resist high voltages.
However, the MOS transistors Q
51
, Q
52
, Q
61
, Q
62
must undergo a special process to form the thick gate oxidation films. This complicates the manufacturing process and increases manufacturing cost.
SUMMARY OF THE INVENTION
It is a first object of the present invention to provide an output circuit that inhibits the flow of a leakage current from the output terminal to the power supply.
It is a second object of the present invention to provide an output circuit that is not required to resist high voltages.
To achieve the above objects the present invention provides an output circuit having an output terminal. The output circuit includes at least one p-channel MOS transistor connected between the output terminal and a high potential power supply, and having a back gate, and a first switch circuit connected between the at least one p-channel MOS transistor and the high potential power supply. The first switch circuit selectively connects and disconnects the back gate of the at least one p-channel MOS transistor and the high potential power supply in response to an external signal applied to the output terminal.
Another aspect of the present invention provides an output circuit having an output terminal. The output circuit includes at least one p-channel MOS transistor connected between the output terminal and a high potential power supply, and a switch circuit connected between a gate of the at least one transistor and the output terminal. The switch circuit connects the gate of the at least one p-channel MOS transistor to the output terminal in response to an external signal applied to the output terminal.
A further aspect of the present invention provides an output circuit having an output terminal. The output circuit includes a plurality of p-channel MOS transistors connected between the output terminal and a high potential power supply, a plurality of n-channel MOS transistors connected between the output terminal and a low potential power supply, and a voltage generating circuit connected to a gate, which is located close to the output terminal, of one of the p-channel MOS transistors and the n-channel MOS transistors. The voltage generating circuit adjusts the potential appli

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