Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-04-01
2001-01-09
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S027000, C326S057000
Reexamination Certificate
active
06172527
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to an output circuit, particularly to an output circuit capable of taking out three states of an output terminal, namely, a power supply voltage level, ground voltage level and a high impedance state.
2. Description of the Related Art
In a semiconductor integrated circuit, there is provided an output circuit for driving a load of an external circuit that operates in response to an output signal from the semiconductor integrated circuit and a wiring having a large load capacitor in the semiconductor integrated circuit. Accordingly, transistors constituting the output circuit have a large driving capacity compared with general transistors constituting the semiconductor integrated circuit.
An output stage of the output circuit is generally composed of two transistors that are serially connected with each other between a power supply voltage supply terminal (referred to as power voltage supply terminal) and a ground voltage supply terminal, wherein the connecting point of these transistors forms an output terminal. With such a construction, there occurs a timing when these two transistors are conducted, thereby producing a feedthrough current. Since the output circuit employs transistors having such a large driving capacity, the feedthrough current becomes large. The feedthrough current in such an output circuit is to negligible in the semiconductor integrated circuit requiring a low consumption power. As a method of reducing the feedthrough current of the output circuit is disclosed, for example, in the following literature.
Name of literature: Japanese Patent publication No. 8-84057
The aforementioned literature employs a NAND gate or a NOR gate wherein a timing when one or both signals having complementary voltage levels are inputted to the NAND gate or the NOR gate in delayed by an inverter to render both transistors nonconductive, then to render one transistor conductive. With such a construction, two transistors constituting an output stage of the output circuit does not become conductive at the same time.
In the method disclosed in the aforementioned literature, an output signal of the output stage always generates a high impedance state for the time corresponding to the delay time by the inverter. Accordingly, even in a timing when feedthrough current is not produced depending on two input signals inputted to the output circuit, the high impedance state is always generated for a given time. Accordingly, high speed responsivity of the output circuit is to always satisfied.
As viewed from input terminals of the output circuit to which signals are inputted, there occurs delay in the operation of the output stage by the time involved in passing through the NAND gate or NOR gate in addition to the delay by the inverter. In this case, if a noise is generated in the signal inputted to the output circuit, the state of the output signal from the output circuit is stabilized after it is temporarily rendered to a high impedance state via the inverter, the NAND gate or NOR gate.
It is an object of the invention to solve the aforementioned problems and provide an output circuit capable of reducing a feedthrough current in the output stage of the output circuit without deteriorating the high speed responsivity.
It is another object of the invention to provide an output circuit capable of reducing the increase of the number of elements as much as possible, thereby achieving the above object.
It is still another object of the invention to provide an output circuit capable of achieving the above object even if a noise is generated in signals to be inputted thereto.
SUMMARY OF THE INVENTION
To achieve the above objects, in an output circuit for outputting an output signal that is set to either first voltage level, or second voltage level or high impedance state in response to voltage levels of first and second data signals according to the invention, the output circuit comprises a first gate circuit that is connected with a first node to which a first signal having a voltage level which is set at least by one voltage level of either first or second data signal is transmitted, and that shapes a waveform to the first signal, a second gate circuit that is connected with a second node to which a second signal having a voltage level which is set at least by one voltage level of either first or second data signal is transmitted, and that shapes a waveform of the second signal, a first transistor for electrically connecting a first power voltage supply terminal and an output terminal thereof in response to a voltage level of an output signal of the first gate circuit, a second transistor for electrically connecting a second power voltage supply terminal and an output terminal thereof in response to a voltage level of the output signal of the second gate circuit, a first control circuit for applying a voltage, that renders the first transistor nonconductive in response to a voltage level of the second node, to a gate electrode of the first transistor, a second control circuit for applying a voltage, that renders the second transistor nonconductive in response to a voltage level of the first node, to a gate electrode of the second transistor, wherein the first gate circuit is selectively set to a state capable of outputting the first signal that has been shaped in waveform, or to a high impedance state in response to the voltage level of the second node, and wherein the second gate circuit is selectively set to a state capable of outputting the second signal that has been shaped in waveform, or to a high impedance state in response to the voltage level of the first node.
Further, the output circuit of the invention may include a plurality buffers circuits provided between the output terminal of the first gate circuit and the gate electrode of the first transistor, and a plurality of buffer circuits provided between the output terminal of the second gate circuit and the gate electrode of the second transistor.
Still further, the output circuit of the invention may have the first signal formed of an output signal of a first differential logic circuit and the second signal formed of an output signal of a second differential logic circuit.
Still more further, the output circuit of the invention may include the first differential logic circuit that receives first and second control signals as input signals which are generated in response to the voltage level of the first data signal and the voltage level of the second data signal, and the second differential logic circuit that receives third and fourth control signals as input signals which are generated in response to the voltage level of the first data signal and the voltage level of the second data signal.
REFERENCES:
patent: 5001369 (1991-03-01), Lee
patent: 5173627 (1992-12-01), Lien
patent: 5825215 (1998-10-01), Sugio et al.
patent: 5920210 (1999-07-01), Kaplinsky
patent: 5933025 (1999-08-01), Nance et al.
patent: 5-33417 (1993-02-01), None
patent: 6-267276 (1994-09-01), None
Cho James H.
Jones Volentine, LLC
OKI Electric Industry Co., Ltd.
Tokar Michael
LandOfFree
Output circuit capable of reducing feedthrough current does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Output circuit capable of reducing feedthrough current, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output circuit capable of reducing feedthrough current will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2470897