Output circuit and synchronous semiconductor memory device havin

Details Output circuit and synchronous semiconductor memory device havin Output circuit and synchronous semiconductor memory device havin

1998-07-21

2000-04-18

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, G11C 800

Patent

active

060523298

ABSTRACT:
An output circuit and a synchronous semiconductor memory device according to the invention suppress output of invalid data, and perform data output with exact timings. The synchronous semiconductor memory device includes a plurality of output buffers provided correspondingly to data I/O terminals, a plurality of data transfer latch circuits and a plurality of output control signal latch circuits. Data transfer latch circuit transfers data read from a memory cell to the corresponding output buffer in response to an internal clock signal. The output control signal latch circuit issues an output control signal to the corresponding output buffer in synchronization with the internal clock signal. Thereby, an output timing of each output buffer can be controlled independently of the other output buffer.

REFERENCES:
patent: 5404338 (1995-04-01), Murai et al.
patent: 5535171 (1996-07-01), Kim et al.
patent: 5933379 (1999-08-01), Park et al.
patent: 5953286 (1999-09-01), Matsubara et al.
patent: 5959900 (1999-09-01), Matsubara

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