Output buffering apparatus and method

Details Output buffering apparatus and method Output buffering apparatus and method

1999-07-09

2001-01-09

Phan, Trong (Department: 2818)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S087000

Reexamination Certificate

active

06172516

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer and an output buffering method, and more particularly, to an output buffer which can be used for an integrated circuit.
2. Description of the Related Art
Conventional output buffers have been disclosed in many texts. For example, a conventional output buffer is shown in FIGS. 5-61 on pages 229-230 in a text which was written by Neil Weste and Kamran Eshraghian and published with a title “Principles of CMOS VLSI design” and a subtitle—A systems perspective—in 1985 by the Addison Wesley publishing company.
FIG. 1
shows a conventional output buffer comprised of an output buffer
10
and an output port
20
. The output buffer
10
is comprised of an inverter
12
, a NAND gate
14
, a NOR gate
16
, and PMOS and NMOS transistors MP
0
and MN
0
.
The output buffer
10
of
FIG. 1
, which is used for an integrated circuit, delays input data DA having a logic “high” or “low” level for a predetermined period of time and provides the delayed data to the output port
20
. The output buffer
10
is built in the integrated circuit. Generally, the output buffer
10
is enabled in response to an output enable signal OEB having a logic “low” level. When the input data DA is a logic “high” level, the output buffer
10
applies a source current to a load capacitor (not shown) included in the output port
20
using a pull-up transistor MP
0
and thus charges the load capacitor with the source current, thereby increasing the potential of the output port
20
. When the input data DA is a logic “low” level, the output buffer
10
sinks the current charged into the load capacitor (not shown) of the output port
20
using a pull-down transistor MN
0
, thereby discharging the capacitor and lowering the voltage of the signal output from the output port
20
.
In the circuit of
FIG. 1
, in order to sufficiently drive a load (not shown) connected to the output port
20
, a relatively large amount of current must flow in the pull-up and pull-down transistors MP
0
and MN
0
of the output buffer
10
, as compared to other circuits within a system that uses the output buffer
10
. When such a current passes through the bonding wire and the lead frame of a power supply V
DD
and a ground V
SS
pin, an induced electromotive force [V(t)] expressed by the following Equation 1 is generated:
V
⁡
(
t
)
=
L
⁡
(
ⅆ
i
ⅆ
t
)
,
(
1
)
wherein L denotes inductance and i denotes the current supplied to a load (not shown) connected to the output port
20
. Here, the induced electromotive force causes the ground voltage (or a reference voltage ) V
SS
to bounce. That is, the conventional output buffer
10
has a problem in that a ground bounce effect is caused by the induced electromotive force. Furthermore, as can be seen from Equation 1, ground bounce becomes more serious with an increase in the total amount of inductance or in the variation of current according to time.
Due to the development of semiconductor manufacturing techniques and increases in the operational speed of systems including semiconductors, the size of a load (not shown) to be driven by the single output buffer
10
increases, and the driving speed becomes faster. Hence, the noise and distortion in a buffered signal OUT are increased due to the ground bounce effect and an impedance mismatch between the output port
20
and the output buffer
10
.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide an output buffer capable of reducing noise and distortion of buffered output data while operating at high speed.
It is another object of the present invention to provide a data buffering method for buffering data in the above output buffer.
Accordingly, to achieve the first object, there is provided an output buffer for buffering input data and outputting buffered input data as output data. The output buffer includes first through M-th and (M+1)th through (M+N)th delay means for delaying the input data for (M+N) different delay times and outputting one by one delayed data in a predetermined order at time intervals of
T
M
+
N
,
where M and N are each integers equal to or greater than 2, and T corresponds to the time necessary for the level of the output data to change. The buffer of the invention also includes a data output means for outputting the output data in response to the outputs of the first through (M+N)th delay means.
In accordance with another embodiment of the invention, there is provided an alternative output buffer for buffering input data and outputting buffered input data as output data. This alternative output buffer includes a data input means enabled in response to an output enable signal, to invert the input data and output the inverted input data. The buffer also includes first through fourth delay means for delaying the inverted input data for first, second, third and fourth predetermined times and outputting one by one delayed data in a predetermined order at time intervals of
T
4
,
where T corresponds to the time necessary for the level of the output data to change. First and second pull-up transistors are separately turned on in response to the outputs of the first and second delay means. Each of the first and second pull-up transistors has a source and drain connected between a supply voltage and the output data. First and second pull-down transistors are separately turned on in response to the outputs of the third and fourth delay means. Each of the first and second pull-down transistors has a drain and source connected between the output data and a reference voltage.
In accordance with the invention, there is also provided a buffering method performed in an output buffer for buffering input data and outputting buffered input data as output data. According to the method of the invention, the input data for (M+N) are delayed for different predetermined times. First through (M+N)th delayed data are generated in a predetermined order at time intervals of
T
M
+
N
,
where M and N are each integers equal to or greater than 2, and T corresponds to the time necessary for the level of the output data to change. It is determined whether the input data has changed from a first logic level to a second logic level, wherein the second logic level is complementary to the first logic level. The level of the output data is gradually changed from the first logic level to the second logic level at time intervals of
T
M
+
N
in response to the first through (M+N)th delayed data which are generated in a predetermined order, if the level of the input data changes from the first logic level to the second logic level. The level of the output data is gradually changed from the second logic level to the first logic level at time intervals of
T
M
+
N
in response to the (M+N)th through first delayed data which are generated in a predetermined order, if the level of the input data changes from the second logic level to the first logic level.


REFERENCES:
patent: 4890016 (1989-12-01), Tanaka et al.
patent: 4967110 (1990-10-01), Matsuura
patent: 5036222 (1991-07-01), Davis
patent: 5153450 (1992-10-01), Ruetz
patent: 5194764 (1993-03-01), Yano et al.
patent: 5646543 (1997-07-01), Rainal
patent: 6034548 (2000-03-01), Churcher et al.

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