Output buffer with timing feedback

Details Output buffer with timing feedback Output buffer with timing feedback

1999-05-21

2001-05-22

Pham, Chi (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C327S158000

Reexamination Certificate

active

06236695

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuit output buffers and in particular the present invention relates to integrated circuit output buffer control circuitry.
BACKGROUND OF THE INVENTION
Integrated circuits can be connected to an external communication line, or bus, and traditionally include an output buffer, or driver circuit. An output buffer is typically characterized by a delay time experienced from applying a clock signal to an input of the buffer until valid data is provided at an output. This delay time is often referred to as Tco (time from clock to output). The performance of an integrated circuit/data line communication system is limited (among other things) by the variation in Tco. In general, if Tco is too long then the system operating frequency is reduced to allow time for the driven output to arrive at and set up a receiver connected to a remote end of the communication bus. If the delay is too short, the output may arrive at the receiver too quickly. Thus, variations in Tco need to be controlled to remain between the two limits imposed by the system and its design targets.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an output buffer and circuitry which allows the output buffer delay time to be dynamically controlled.
SUMMARY OF THE INVENTION
In one embodiment, output buffer circuitry comprises an output buffer with a controllable delay time, a reference output buffer with a controllable delay time, and a synchronous delay circuit to provide a reference clock signal to the reference output buffer. The reference clock signal calibrates the delay time of both the reference output buffer and the output buffer to a predetermined delay time.
In another embodiment, a method of adjusting a delay time of an output buffer circuit is described. The method comprises receiving an input clock signal, generating a reference clock signal which has a signal transition delayed by a corresponding transition in the clock signal, the delay is equal to 1/N of a period of the input clock signal, adjusting a delay time of a reference output buffer circuit to be equal to 1/N of the period of the input clock signal, and adjusting the delay time of the output buffer circuit based upon the adjusted delay time of the reference output buffer circuit.


REFERENCES:
patent: 4899071 (1990-02-01), Morales
patent: 5815017 (1998-09-01), McFarland
wolff et al., “Microwave Engineering and Systems Applications”, p. 69, published by John Wiley & Son, 1988.

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