Output buffer with time varying source impedance for driving...

Details Output buffer with time varying source impedance for driving... Output buffer with time varying source impedance for driving...

2005-12-27

2005-12-27

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S021000, C326S136000

Reexamination Certificate

active

06980021

ABSTRACT:
An output buffer for driving a capacitively-terminated transmission line produces a waveform which comprises a first portion during which the waveform transitions from a voltage V1to a voltage V2; a second portion during which it remains fixed at V2; a third portion during which it transitions to a voltage V3; and a fourth portion during which it remains fixed at V3. The waveform is created within a unit interval whenever successive data bits transition between logic states. The first and second portions are generated with circuitry arranged such that V2is maximized by reducing the buffer's output impedance. The fourth portion is generated with circuitry which has a non-zero output impedance preferably equal to the transmission line's characteristic impedance, to absorb transitions reflected back to the source circuitry by the capacitive termination.

REFERENCES:
patent: 6838900 (2005-01-01), Huang et al.
patent: 6917217 (2005-07-01), Herz
patent: 6922075 (2005-07-01), Morley

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