Output buffer with slew rate control and a selection circuit

Details Output buffer with slew rate control and a selection circuit Output buffer with slew rate control and a selection circuit

2006-03-28

2006-03-28

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Pulse shaping

C326S027000

Reexamination Certificate

active

07019551

ABSTRACT:
An output buffer having a controlled output slew rate comprises a first predriver circuit having a first RC circuit and a first output node and a second predriver circuit having a second RC circuit and a second output node. A buffer input node is coupled to the first and second predriver circuits. The output buffer further includes an output circuit having first and second input nodes and a third output node, where the first and second input nodes are coupled, respectively, to the first and second output nodes. The time constants of the RC circuits control a signal slew rate at the third output node of the output circuit, and the value of R may be selected to provide a predetermined, controlled slew rate range at the third output node. A selection circuit aids in the selection of an appropriate value for R.

REFERENCES:
patent: 4622482 (1986-11-01), Ganger
patent: 5218239 (1993-06-01), Boomer
patent: 6236248 (2001-05-01), Koga

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