Output buffer with overvoltage protection

Details Output buffer with overvoltage protection Output buffer with overvoltage protection

2002-05-16

2004-09-28

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C081S037000, C081S121100, C327S318000

Reexamination Certificate

active

06798244

ABSTRACT:

TECHNICAL FIELD
The present invention relates to an input/output buffer design capable of handling multiple types of signals. More particularly, the present invention relates to an output buffer capable of driving loads for different types of circuitry, such as Peripheral Component Interconnect (PCI) circuitry, Gunnings Transceiver Logic (GTL), Emitter Coupled Logic (ECL), Series Stub Terminated Logic (SSTL), or Pseudo Emitter Coupled Logic (PECL) to desired output levels without damaging internal transistors.
BACKGROUND
Circuits constructed in accordance with standards such as PCI, GTL, ECL, SSTL or PECL each have different high and low state characteristics. Although some of the states for different circuit types will have similar voltage and current requirements, others will be different.
PCI provides a high speed bus interface for PC peripheral I/O and memory and its input and output voltage and current requirements are similar to CMOS. For instance, the high and low voltage states will vary from rail to rail (VDD to VSS), with high impedance low current inputs and outputs.
GTL provides a lower impedance higher current high state, providing a low capacitance output to provide higher speed operation. The transition region for GTL is significantly smaller than for CMOS.
PECL provides a high current low voltage to provide a smaller transition region compared to CMOS to better simulate emitter coupled logic (ECL). The PECL offers a low impedance outputs and a high impedance inputs to be the most suitable choice of logic to drive transmission lines to minimize reflections.
Integrated circuit chips, such as a field programmable gate array (FPGA) chip, or a complex programmable logic device (CPLD), provide functions which may be used in a circuit with components operating with any of the logic types, such as PCI, GTL, ECL, PECL, or SSTL described above. The integrated circuits may operate with low voltage transistors. For instance, 1.8 volt transistors may be used which may be damaged by voltages levels significantly higher than 1.8 volts. It would be desirable to have an input/output buffer for use on a general applicability chip such as a FPGA or CPLD to selectively make the chip compatible with any of these logic types while preventing damage to the chip due to overvoltage situations.
SUMMARY
In accordance with the present invention, an input/output buffer circuit includes an output buffer which can selectively be made compatible with any of a number of logic types, such as PCI, GTL, or PECL, while using small transistors, such as 1.8V or 3.3V without damaging the transistors.
In accordance with the present invention, the output buffer portion of the circuit includes an input signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). The signal from the PAD is fed back through an input buffer circuit which can be programmably set to operate in one of a GTL, PECL, or PCI operation modes to provide a signal to a node (INB). The node (INB), then is provided to switches to enable the output buffer to rapidly transition the PAD, and to prepare for subsequent transitions of the PAD after another transition of the input D.
The circuitry of the output buffer further provides necessary drive current to transition a load at a desired rate and to set output voltage limits, while limiting drive current after switching to enable a subsequent rapid output transition. The output buffer includes pull up PMOS transistors with source-drain paths connecting VDD to the PAD. The gates of the pull-up PMOS transistors are driven by switching circuits including numerous PMOS transistors included in a common well with the pull up PMOS transistors.
Components in the switching circuitry are provided to connect the PAD to VSS when the PAD voltage exceeds the power supply voltage VSS. Further, the switching circuitry includes components to connect the common wells of PMOS transistors to VSS when the common well has a charge buildup exceeding exceeds VDD.


REFERENCES:
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patent: 6028758 (2000-02-01), Sharpe-Geisler
patent: 6031365 (2000-02-01), Sharpe-Geisler
patent: 6255850 (2001-07-01), Turner
patent: 6265926 (2001-07-01), Wong
U.S. patent application Ser. No. 10/146,739, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/146,826, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/146,769, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/147,199, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/146,734, Sharpe-Geisler, filed May 16, 2002.
U.S. patent application Ser. No. 10/147,011, Sharpe-Geisler, filed May 16, 2002.

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