Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Patent
1997-01-27
1998-11-03
Santamauro, Jon
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
326 87, 326 57, H03K 1716, H03K 19094
Patent
active
058314474
ABSTRACT:
An output buffer array to a data output device in an integrated circuit. The output buffer array includes a plurality of output buffers connected together to a pair of parallel connected first and second voltage lines connected to a voltage supply circuit supplying a first voltage representative of a first logic state, and also to a pair of parallel connected first and second grounding lines connected to a grounding circuit supplying a second voltage representative of a second logic state. Each output buffer further includes logic and switching means which are devised in such a manner as to allow the noise occurred in one voltage or grounding line during the switching of the input data from one logic value to another to be dumped into another line such that the voltage transferred to the output of the output buffer is free from noise. This also allows the effect of ground bounce to be significantly reduced. These benefits allow the output buffer array to operate stably and reliably to offer the desired performance.
REFERENCES:
patent: 5121013 (1992-06-01), Chuang et al.
patent: 5204554 (1993-04-01), Ohannes et al.
patent: 5319260 (1994-06-01), Wanlass
patent: 5332932 (1994-07-01), Ranaldue
patent: 5438277 (1995-08-01), Sharpe-Geisler
patent: 5534791 (1996-07-01), Mattos et al.
Le Don Phu
Santamauro Jon
United Microelectronics Corp.
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