Output buffer with digital slew control

Details Output buffer with digital slew control Output buffer with digital slew control

2006-12-21

2008-10-28

Cho, James H (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Pulse shaping

C326S030000

Reexamination Certificate

active

07443192

ABSTRACT:
An improved output buffer having a digital output slew control and compensation for manufacturing process variations. Output slewing is accomplished by sequencing digital drive signals to paralleled output transistors. In one embodiment, a pre-driver sequences the drive signals by using the propagation delays of serially coupled digital logic gates to reduce power supply droop and/or ground bounce. The output transistors are turned off substantially simultaneously to avoid undesirable power supply DC current flow when the output buffer changes state. Programmably configuring the number of paralleled transistors that may be turned on at any given time allows a user to compensate for manufacturing process variations and determine the output impedance/drive capacity of the buffer.

REFERENCES:
patent: 5838186 (1998-11-01), Inoue et al.
patent: 5859552 (1999-01-01), Do et al.
patent: 6480026 (2002-11-01), Andrews et al.
patent: 6967500 (2005-11-01), Lin et al.
patent: 7009433 (2006-03-01), Zhang et al.

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