Output buffer with control circuitry

Details Output buffer with control circuitry Output buffer with control circuitry

2000-08-02

2002-04-02

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

C326S083000, C326S086000

Reexamination Certificate

active

06366114

ABSTRACT:

BACKGROUND
The present invention relates generally to integrated circuits. More particularly, the present invention relates to an output control circuit for use to reduce power or ground bounce noise, or both.
Digital logic circuits are widely used in the areas of electronics and computer-type equipment. One such use of digital logic circuits is to provide an interface function between one integrated circuit chip and another integrated circuit chip. An output buffer is an important component for performing this interface function. The output buffer generates, when enabled, an output signal which is a function of a data signal received from internal logical circuitry of the integrated circuit.
An output buffer circuit typically uses a pull-up transistor connected in series between first and second power supply terminals. The first power supply terminal maybe supplied with a positive potential which is connected to a power supply potential node. The second power supply terminal may be supplied with a ground potential, which is connected to a ground potential node. The connection point of the pull-up and pull-down field-effect transistors is further joined to an output terminal.
Dependent upon the logic state of the data input signal (and an output enable signal for a tristateable output buffer), either the pull-up or pull-down transistor is quickly turned on and the other one of them is turned off. Such rapid switching on and off the pull-up and pull-down transistors causes sudden surges of current creating what is commonly known as current spikes. These current spikes will flow through the impedance and inductive components of power supply lines so as to cause inductive noise at the internal power supply potential and the internal ground potential nodes of the output buffer. In particular, when the pull-down transistor is quickly turned on a large instantaneous current cooperates with the line inductance to pull up the internal ground potential which is defined as “ground bounce noise.” The line inductance and resistance may be a parasitic artifact from the bonding wires and lead frame.
Similarly, when the pull-up transistor is turned on too quickly, there may be “power bounce noise” on the power potential.
Therefore, it is desirable to provide an output current control circuit for use with an output buffer which reduces ground bounce and power bounce noise, but yet provides high speed of operation.
SUMMARY OF THE INVENTION
The present invention provides techniques and circuits for reducing noise at the output of an integrated circuit. In an embodiment, the present invention is an output buffer with control circuitry to reduce ground or power noise, or both. The output buffer includes a ramp control circuit and di/dt detect circuit.
The ramp circuit provides an output for driving an output driver of the integrated circuit. The slew rate of the ramp circuit output is controlled by the di/dt detect circuit. The di/dt detect circuit monitors the noise at the supply node (e.g., power or ground). When the noise is above a threshold value, the di/dt detect circuit provides a signal to the ramp circuit to slow the slew rate of the ramp circuit output. A slower slew rate on the ramp circuit corresponds to a slower slew rate for the output driver. This will reduce noise on the supply node.
The circuitry of the present invention may also increase the slew rate of the ramp circuit when the noise is below a threshold value. This will increase the slew rate at the output of the integrated circuit, and will generally provide performance benefits.
In a specific embodiment, a ramp control of the output buffer is controlled by a di/dt or supply noise detect circuit. When the di/dt detector detects a di/dt level from a tranisistor coupled to a control electrode of the output driver, a signal if provided to the ramp control circuit to slow the ramp of the output driver. This limits the supply noise to a level, which may be specified by the design. The di/dt detector may also signal the ramp control to speed up when the di/dt drops below a certain level.
An aspect of the present invention is an output buffer including a pull-down driver coupled between an output node and a ground potential; a ramp control circuit coupled between a logical input signal and a control electrode input to the pull-down driver, where the ramp control has an input coupled to the output node; and a ground noise detect circuit coupled to the ground electrode, and coupled to control the ramp circuit to decrease a slew rate of a low-to-high transition of a signal applied to the control electrode input to the pull-down driver in response to ground noise above a threshold value at the ground electrode.
A further aspect of the invention is output buffer including a pull-down driver having a control electrode; and a control circuit. The control circuit includes a first transistor having a gate coupled to the control electrode of the pull-down driver, where a source electrode of the first transistor is coupled to a ground potential; a second transistor, diode-connected and coupled between the first transistor and the ground potential; and a third transistor, diode-connected and coupled between a power potential and the first and second transistors.
An even further aspect of the present invention is a method of reducing noise at an output of an integrated circuit. An output driver is coupled to a supply and the output of the integrated circuit. A ramp circuit provided to drive a control electrode of the output driver. A noise detection circuit is provided to monitor noise at the supply. A signal from the noise detection circuit is provided to increase a slew rate of a signal from the ramp circuit when the noise is below a threshold value.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.


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