Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-12-18
2003-03-18
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
Reexamination Certificate
active
06535020
ABSTRACT:
BACKGROUND
1. Field of Invention
This invention relates generally to digital logic systems and specifically to maintaining specified performance characteristics over process and temperature variations.
2. Description of Related Art
Modern electronic devices such as personal computers typically include a plurality of integrated circuit (IC) or semiconductor chips that communicate with each other, for example, via a common bus. Typically, each IC chip includes an output driver to drive signals from the IC chip onto the bus, or alternately, directly onto one or more other IC chips. The rate at which an output driver transitions a signal (e.g., logic low to logic high) is known as its slew rate, which is typically measured in volts per unit of time. In order to ensure circuit speed compatibility between IC chips and associated buses, the output drivers used in the IC chips should adhere to a specified slew rate range. If the specified slew rate is not met by an output driver, its host IC chip may not operate at the specified frequency, and may become incompatible with other chips or devices. Further, although higher operating frequencies are generally desired, if the slew rate is too high, e.g., the output driver charges the output signal too quickly, undesirable noise may be introduced into the output signal. As a result, it is important for the output drivers to maintain the specified slew rate at all times.
Conventional output drivers have several limitations.
First, as the physical dimensions of IC chips become smaller, it becomes more difficult to control the operating characteristics (e.g., slew rates) of the transistors therein. Process variations inherent in the fabrication of semiconductor chips often cause transistors of the same design to behave differently. For example, the amount of current provided by a transistor, which affects its slew rate, is dependent upon a number of factors including, for example, transistor size, gate-to-source voltage (V
GS
), and manufacturing-related parameters. Although transistor size and V
GS
may be precisely controlled, manufacturing process characteristics typically vary between transistors because, for example, of imperfections in available doping technologies. Indeed, because implant doping is a chemical process performed over time, variations in dopant concentrations between transistors, especially between transistors fabricated from different wafers, are inevitable. These variations are even more pronounced for smaller devices, and may result in significant operating characteristic variations. As a result, output drivers of the same design and having the same specified operating characteristics may undesirably operate at different speeds, and therefore may have slew rates different from those specified.
Further, transistor operating characteristics vary with changes in temperature. Typically, transistors tend to operate more slowly as the IC chip heats up and, conversely, tend to operate more quickly as the IC chip cools down. As a result, the slew rate of conventional output drivers undesirably varies with temperature. Accordingly, changes in the operating temperature of an output driver may cause the output driver's slew rate to drift from its specified slew rate. This, in turn, may lead to unwanted noise and/or incompatibility with other devices.
Thus, there is a need for an improved output driver that maintains a specified slew rate over process and temperature variations of the drive transistor.
SUMMARY
A method and apparatus are disclosed that compensate for process and temperature variations in the drive transistor(s) of a circuit in order to maintain a specified slew rate that is independent of such process and temperature variations in the drive transistor(s). In accordance with the present invention, a circuit includes a drive transistor coupled between an output and a first potential, a constant current circuit coupled between the gate of the drive transistor and a second potential, and a compensation circuit coupled between the gate of the drive transistor and the first potential. The constant current circuit uses a constant current that is substantially independent of process and temperature variations to turn on the drive transistor at a constant rate, regardless of process and temperature variations. The compensation circuit provides a small compensation current that cancels some of the constant current and, thus, slightly decreases the turn-on rate of the drive transistor. The compensation current is dependent upon process and temperature variations of the drive transistor, and therefore reduces the turn-on rate of the drive transistor according to process and temperature variations of the drive transistor. In this manner, the output maintains a constant specified slew rate that does not drift in response to process and temperature variations in the drive transistor.
For one embodiment, the drive transistor is a PMOS transistor coupled between an output and a supply voltage, the constant current circuit is an NMOS pull-down transistor coupled between gate of the drive transistor and ground potential, and the compensation circuit is a PMOS transistor coupled between the gate of the drive transistor and the supply voltage. The pull-down transistor, which is controlled by a bias circuit, provides a current that is substantially independent of process and temperature variations, and therefore operates to discharge the gate of the PMOS drive transistor at a constant rate, regardless of process and temperature variations. The compensation transistor conducts a small current that cancels some of the constant current that discharges the gate of the drive transistor. The PMOS compensation transistor models the PMOS drive transistor, and thus tracks process and temperature variations in the drive transistor. Accordingly, the compensation current, which is dependent upon process and temperature variations of the drive transistor, adjusts the discharge rate of the gate of the PMOS drive transistor in response to process and temperature variations therein in order to maintain the specified output slew rate.
For example, if the drive transistor is weaker than normal due to process and/or temperature variations, and thus the output would ordinarily have a lower slew rate than specified, the compensation transistor is also weaker than normal, and thus conducts a weaker compensation current. The weaker compensation current cancels less of the constant discharge current than normal, thereby increasing the discharge rate of the gate of the drive transistor, which in turn increases the output slew rate back toward its specified value. Conversely, if the drive transistor is stronger than normal due to process and/or temperature variations, and thus the output would ordinarily have a higher slew rate than specified, the compensation transistor is also stronger than normal, and thus conducts a stronger compensation current. The stronger compensation current cancels more of the constant discharge current than normal, thereby decreasing the discharge rate of the gate of the drive transistor, which in turn decreases the output slew rate back toward its specified value.
For other embodiments, the drive transistor is an NMOS transistor coupled between the output and ground potential, the constant current circuit is a PMOS pull-up transistor coupled between gate of the drive transistor and the supply voltage, and the compensation circuit is an NMOS transistor coupled between the gate of the drive transistor and ground potential. For such embodiments, the NMOS compensation transistor is modeled after and tracks process and temperature variations in the NMOS drive transistor, thereby adjusting the output slew rate for process and temperature variations in the NMOS drive transistor by effectively canceling an amount of the charge current provided by the pull-up transistor in response to such process and temperature variations.
REFERENCES:
patent: 4857770 (1989-08-01), Partovi et al.
patent: 5568081 (1996-10-01), Lui et al.
patent: 562321
Le Don
M & P, LLP
Paradice III William L.
Sun Microsystems Inc.
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