Output buffer slew rate control using clock signal

Details Output buffer slew rate control using clock signal Output buffer slew rate control using clock signal

2007-04-10

2007-04-10

Le, Don (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S083000

Reexamination Certificate

active

10732687

ABSTRACT:
A signal generated by circuitry for an output buffer is identified relative to a clock signal to control a slew rate of the circuitry for an output buffer.

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