Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-03-13
2003-04-01
Lee, Michael G. (Department: 2876)
Electronic digital logic circuitry
Interface
Current driving
C326S056000, C326S112000, C326S083000, C327S539000
Reexamination Certificate
active
06542004
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to a method and/or architecture for implementing an output buffer, and more particularly, to a method and/or architecture for implementing a high speed output buffer with ON resistance and skew control.
BACKGROUND OF THE INVENTION
Conventional approaches for implementing output buffers use a pre-buffer section to control rise and fall rates of gate voltages. Referring to
FIG. 1
, a schematic of a circuit illustrating such an approach is shown. The circuit
10
comprises a pre-buffer
12
and an I/O circuit
14
. The pre-buffer
10
comprises a current source I
1
, a current source I
2
, a number of MOSFETs P
1
-P
8
and a number ofMOSFETs N
1
-N
8
. The circuit
10
receives the signal IN. The circuit
10
generates the signal OUT
1
and the signal OUT
2
. A current on the signals OUT
1
and OUT
2
(presented, for example, to output capacitors C
1
and C
2
) has the relationship i=cdv/dt. By limiting the transient current of the signals OUT
1
and OUT
2
, by controlling a turn on rate of the MOSFETs P
7
, N
7
, P
8
and N
8
, the likelihood of rapid rates of change of current in the power and ground inductances is reduced. In turn, a ground or power bounce voltage via the relationship v=ldi/dt is reduced. The pre-buffer section
12
also causes the output device P
7
connected to the output OUT
1
to shut off before the MOSFET N
7
turns on, limiting crowbar current in the MOSFET P
7
and the MOSFET N
7
. The pre-buffer
12
operates as follows: (i) if the MOSFET P
7
is on and the MOSFET N
7
is off, then the MOSFET N
3
, the MOSFET N
4
and the MOSFET N
5
are on, while the MOSFET P
2
remains off; (ii) if the signal IN goes high, the MOSFET N
3
and the MOSFET N
5
turn off immediately, while the MOSFET P
2
turns on fast and the MOSFET P
7
shuts off fast. At the same time, the MOSFET N
6
turns off fast and the MOSFET P
6
begins to pull the gates of the MOSFET N
8
and N
7
high. The gates of the MOSFET N
7
and N
8
are pulled high slowly, since the MOSFET P
6
is a weak MOSFET.
The weak MOSFET P
6
is also assisted by the current source I
2
and a current mirror (i.e., the MOSFET P
3
, the MOSFET P
4
, and the MOSFET P
5
). When the weak MOSFET P
6
is assisted by the current mirror, the MOSFET P
7
and the MOSFET P
8
turn off fast, while the MOSFET N
7
and the MOSFET N
8
turn on slowly. The MOSFET N
7
, the MOSFET N
8
turn off fast in the opposite direction with the MOSFET P
7
and the MOSFET P
8
turting on slowly.
The MOSFET N
5
and P
6
are sized to barely operate correctly in the fast process, temperature and VCC corner. In the slow comer, the current sources I
1
and I
2
supply additional current drive to ensure proper operation. The voltage rate of change at the gates of the output MOSFETs P
7
, N
7
, P
8
and N
8
is as slow as possible during turn on, while still maintaining conrect operation. The pre-buffer
12
requires the current sources I
1
and I
2
to vary with temperature and supply variations. The current sources I
1
and I
2
are made temperature and supply dependent to enable the pre-buffer section
12
to operate correctly. The temperature and supply dependencies are implemented to ensure a slow enough turn on of the output MOSFETs P
7
and N
8
, while still ensuring operation in the slow comer.
Conventional pre-buffers are very difficult to design and optimize. Likewise, conventional pre-buffers require significant updating with each new process version. Additionally, if an inverting scheme is to be implemented, then accurate matching of P and N channel MOSFETs is required for accurate skew and duty cycle performance. Furthermore, the accurate matching of P and N channel MOSFETs is not practical.
SUMMARY OF THE INVENTION
Controlling ground/power bounce at high frequencies is a substantial problem common to all higher frequency integrated circuits (IC's). The present invention provides a control voltage generator coupled to a pre-buffer which is coupled to an output driver. Together these three functional groups allow a single control voltage generator to be utilized even where multiple outputs are required.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing a high speed, low skew, low voltage (e.g., transistor-transistor logic (TTL)) output buffer with optional inverting capability that may (i) provide a charge to discharge of an output device that may be less process dependent, (ii) provide current sources that may be derived from a single bandgap source (e.g., allowing slow charge and discharge times to be better matched), (ii) allow the current sources to be derived by forcing an internally generated bandgap voltage across an external resistor to generate current sources that may not be dependent on a process absolute resistor value, (iv) allow the current sources to be VCC, process and temperature dependent to further reduce signal variation, (v) provide a well controlled duty cycle for an inverted implementation, (vi) provide controlled ramp rates and voltage levels allowing for slew control and output ON resistance control, (vii) provide low skew, and/or (viii) reduce ringing and power/ground bounce.
REFERENCES:
patent: 4701641 (1987-10-01), Harris et al.
patent: 4723108 (1988-02-01), Murphy et al.
patent: 4877978 (1989-10-01), Platt
patent: 4978905 (1990-12-01), Hoff et al.
patent: 5013940 (1991-05-01), Ansel
patent: 5619163 (1997-04-01), Koo
patent: 5900772 (1999-05-01), Somerville et al.
patent: 6037803 (2000-03-01), Klein
patent: 6236237 (2001-05-01), Wong et al.
patent: 6323801 (2001-11-01), McCartney et al.
Cypress Semiconductor Corp.
Lee Michael G.
Paik Steven S.
Suiter & Associates PC
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