Output buffer incorporating shared intermediate nodes

Details Output buffer incorporating shared intermediate nodes Output buffer incorporating shared intermediate nodes

1996-11-22

1998-02-10

Westin, Edward P.

Electronic digital logic circuitry

Accelerating switching

326 58, 326 83, H03K 190948

Patent

active

057173427

ABSTRACT:
An output buffer is disclosed for an integrated circuit having a varying number of simultaneously switching outputs. As fewer outputs on the integrated circuit are simultaneously switching, the output conductance of certain logic gates within each of the output buffers on the integrated circuit is increased by sharing intermediate nodes between each of the output buffers. Consequently, the speed of the output buffer increases as fewer of the outputs simultaneously switch and internally generated noise is small. Conversely, as additional outputs simultaneously switch, the output conductance of certain logic gates within the output buffer is decreased, resulting in reduced speed of the output buffers and a corresponding reduction in internally generated noise.

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R. Senthinathan and J.L. Pierce, "Application Specific CMOS Output Driver Circuit Design Techniques to Reduce Simultaneous Switching Noise", IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1383-1388 .

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