Output buffer having transmission gate and isolated supply termi

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction

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326 34, 326 57, H03K 1716

Patent

active

055921043

ABSTRACT:
An output buffer having a data input terminal, a data output terminal, a predriver stage, an output stage and a resistive device. The predriver stage includes a first pull-up transistor and a first pull-down transistor which have control terminals coupled to the data input terminal and have first and second outputs, respectively. The output stage includes a second pull-up transistor and a second pull-down transistor which have control terminals coupled to the first and second outputs, respectively, and have third and fourth output terminals coupled to the data output terminal. The resistive device is coupled between the control terminals of the second pull-up and pull-down transistors.

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patent: 5034629 (1991-07-01), Kinugasa et al.
patent: 5140194 (1992-08-01), Okitaka
patent: 5210449 (1993-05-01), Nishino et al.
patent: 5281869 (1994-01-01), Lundberg
patent: 5300829 (1994-04-01), Lev et al.
patent: 5355028 (1994-10-01), O'Toole
patent: 5355029 (1994-10-01), Houghton et al.
patent: 5436577 (1995-07-01), Lee

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