Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2000-01-07
2003-06-10
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C713S500000, C713S330000, C326S083000, C326S087000, C327S100000, C327S112000, C327S322000
Reexamination Certificate
active
06578156
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an output buffer circuit that is suitable for outputting a signal at a low transfer speed, and a master slice type semiconductor device and an electronic apparatus using the output buffer circuit.
2. Description of Related Art
Universal Serial Bus (USB) is a known standard for connecting a personal computer to peripherals. Details of the standard are described in the Universal Serial Bus Specification Revision 1.0.
The USB standard specifies two different data transfer speeds, namely, a full speed (at 12 Mbps) and a low speed (at 1.5 Mbps). The USB standard also specifies electrical characteristics required by an output buffer circuit for low speed, in which the rise time and the fall time of the waveform of an output are specified to be within a range of 75-300 ns for a wide range of load capacitances ranging from 50 to 350 pf.
Conventionally, an output buffer circuit that realizes the low transmission speed of the USB is composed of a bias voltage circuit using resistors and an output driver circuit using a feedback by the capacitance. This structure is disclosed to the public by the Intel Corporation in the U.S.
FIG. 14
is a circuit diagram of a conventional common output buffer circuit that realizes the low transmission speed of the USB. A bias voltage generation circuit
400
is composed of P-type MOS transistors
401
and
402
, resistors R
1
and R
2
, and N-type MOS transistors
403
and
404
. The bias voltage generation circuit
400
generates three types of bias voltages when an enable signal
410
is at a low level.
An output driver circuit
420
is composed of comparators
421
and
422
, a capacitance C, P-type MOS transistors
423
-
426
, and N-type MOS transistors
427
-
430
. The P-type MOS transistor
426
and the N-type MOS transistor
430
, that are provided at an output stage and form a CMOS transistor, are turned on and off by input signals
412
and
414
, respectively. The comparators
421
and
422
and the capacitance C form an output feed back circuit, and control changes in output voltages.
The output buffer circuit shown in
FIG. 14
requires high precision in the resistors R
1
and R
2
and the capacitor C. Therefore, it is difficult to form the output buffer circuit by gate arrays, and conventionally, a custom design is required to realize an output buffer circuit.
Further, circuit tuning of the output buffer circuit shown in
FIG. 14
is difficult. Accordingly, conventional output buffer circuits that achieve the low data transfer speed of the USB require a great number of process steps and costs.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an output buffer circuit that brings the rise time and the fall time of an output signal within a predetermined range for a wide range of capacitance loads, without using resistors or capacitors. It is also an object of the present invention to provide a master slice type semiconductor device and an electronic apparatus using the output buffer circuit.
An output buffer circuit in accordance with one embodiment of the present invention comprises a signal output line and a plurality of switching circuits connected to the signal output line at different locations thereof. Each of the plurality of switching circuits comprises a first switching device connected between a power source line and the signal output line, a second switching device connected between the signal output line and a ground line, a first control signal line that turns the first switching device on and off, and a second control signal line that turns the second switching device on and off. The first switching device and the second switching device in one of the plurality of switching circuits have a minimum current drivability, and the first switching device and the second switching device in another of the plurality of switching circuits have a maximum current drivability.
In accordance with the embodiment, all of the second switching devices are turned off, and the first switching devices are successively turned on in the order from one having a lower current drivability. As a result, the signal level on the signal output line can rise smoothly within a specified time range, when the load capacitance coupled to the signal output line is either low or high. On the other hand, all of the first switching devices are turned off, and the second switching devices are successively turned on in the order from one having a lower current drivability. As a result, the signal level on the signal output line can fall smoothly within a specified time range, when the load capacitance coupled to the signal output line is either low or high. Compared to a circuit that has a pair of switching circuits or a plurality of switching circuits having the same current drivability, the present invention is more effective in implementing a smooth transition of the signal level, and in controlling the signal transition time to be within a predetermined time range for both a low load capacitance and a high load capacitance.
In accordance with one embodiment of the present invention, the plurality of switching circuits may further include another switching circuit composed of the first switching device and the second switching device having a current drivability equal to the minimum current drivability, the maximum current drivability or a current drivability between the minimum current drivability and the maximum current drivability.
By increasing the number of switching circuits, the signal level can be changed more smoothly for both the low load capacitance and the high load capacitance.
In accordance with one embodiment of the present invention, each of the first switching device and the second switching device disposed in each of the plurality of switching circuits is composed of at least one P-type MOS transistor and at least one N-type MOS transistor, respectively, that compose a CMOS transistor.
In this case, the CMOS transistors in the respective switching circuits may be provided with different sizes to achieve the different current drivabilities.
Also, the CMOS transistor in at least one of the plurality of switching circuits has a low current drivability that is attained by connecting a plurality of the P-type MOS transistors and/or the N-type MOS transistors in series to one another. Alternatively, the CMOS transistor in at least one of the plurality of switching circuits has a high current drivability that is attained by connecting a plurality of the P-type MOS transistors and/or the N-type MOS transistors in parallel with one another.
In accordance with one embodiment, the output buffer circuit may be further provided with a predriver circuit that supplies a control signal to the first control signal line and the second control signal line connected to each of the plurality of switching circuits based on an input signal and a clock signal. When the potential on the output signal line is turned to a high level, the predriver circuit turns off all the second switching devices in the plurality of switching circuits and simultaneously turns on the first switching device in the switching circuit having the minimum current drivability. Subsequently, it turns on the first switching devices in the other switching circuits in the order from one having a lower current drivability.
When the potential of the output signal line is turned to a low level, the predriver circuit turns off all the first switching devices in the plurality of switching circuits and simultaneously turns on the second switching device in the switching circuit having the minimum current drivability. Subsequently, it turns on the second switching devices in the other switching circuits in the order from one having a lower current drivability.
An enable signal may be inputted in the predriver circuit. When the enable signal is non-active, the first and the second switching devices in all of the switching circuits are simultaneously turned off to set the signal output l
Hogan & Hartson LLP
Lee Thomas
Seiko Epson Corporation
Trujillo James K.
LandOfFree
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