Output buffer for high and low voltage bus

Details Output buffer for high and low voltage bus Output buffer for high and low voltage bus

1999-09-10

2003-01-28

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S328000, C327S333000, C327S391000

Reexamination Certificate

active

06512401

ABSTRACT:

BACKGROUND
1. Field
This disclosure is related to an output buffer and, more particularly, to an output buffer for an integrated circuit (IC) chip capable of interfacing to either one of a high and a low voltage bus or both.
2. Background Information
One problem that presents itself when coupling integrated circuit chips or IC's together is electrical compatibility. Typically, the integrated circuit chips are designed to operate at a particular input/output (I/O) voltage level or substantially within a particular restricted range of voltage levels. However, with advances in technology, the voltage levels at which integrated circuit chips operate, including for I/O, has been generally decreasing. Unfortunately, the trend for reducing voltages has been considerably faster for core logic, e.g., logic which does not interface to circuits outside the chip, than for I/O, e.g., circuits which primarily interface between chips. Consequently, recent ICs typically support I/O voltage levels which are higher than the core logic voltage levels. This allows for improved performance of the core independent of the support of legacy I/O voltage levels.
This general trend in the reduction of the I/O voltage levels may be an issue when designing or producing an integrated circuit chip. For example, an integrated circuit chip may be designed to operate with relatively high voltage signal levels. In this situation, the integrated circuit chip may not reach state-of-the-art performance levels, as measured by speed, power, and or both, for example, if designed to utilize high voltage tolerant transistors exclusively, although it will likely be compatible with legacy integrated circuit chips. Alternatively, the integrated circuit chip may operate at relatively low voltage levels and, therefore, be compatible with the voltage levels for state-of-the art integrated circuit chips, but may not be amenable to interfacing with legacy integrated circuit chips. For example, currently, but with no loss of generality, voltage levels of approximately 1.8 volts to approximately 3.3 volts may be considered relatively high, while voltage levels up to approximately 1 volt may be considered relatively low. It would be desirable if an approach or technique for producing or designing an integrated circuit chip provided the capability to address this issue.
SUMMARY
Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the circuit configurations. The respective circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.
Briefly, in accordance with another embodiment of the invention, an output buffer includes: a plurality of thick gate metal-oxide semiconductor (MOS) transistors coupled in a circuit configuration. The plurality includes, as pull-up transistors, at least a thick gate PMOS transistor and a thick gate NMOS transistor, both respectively being coupled between separate voltage supply voltage level ports and an output port of the output buffer. The plurality further includes, as pull-down transistors, at least two more thick gate NMOS transistors, both respectively being coupled between ground and the output port. At least one of the pull-up transistors and one of the pull-down transistors is coupled in the circuit configuration to be driven on hard and to deliver a high voltage swing. Furthermore, at least one of the pull-up transistors and one of the pull-down transistors is coupled in the circuit configuration to be driven on less hard and to deliver a reduced voltage swing.


REFERENCES:
patent: 4038564 (1977-07-01), Hakata
patent: 4408135 (1983-10-01), Yuyama et al.
patent: 4731553 (1988-03-01), Van Lehn et al.
patent: 4853560 (1989-08-01), Iwamura et al.
patent: 5095230 (1992-03-01), Takai et al.
patent: 5097152 (1992-03-01), Kohda et al.
patent: 5341045 (1994-08-01), Almulla
patent: 5399918 (1995-03-01), Taylor et al.
patent: 5739700 (1998-04-01), Martin
patent: 5748303 (1998-05-01), Korta et al.
patent: 5811991 (1998-09-01), Takashima
patent: 5830795 (1998-11-01), Mehta et al.
patent: 5859450 (1999-01-01), Clark et al.
patent: 5894238 (1999-04-01), Chien
patent: 5914618 (1999-06-01), Mattos
patent: 5939936 (1999-08-01), Beiley et al.
patent: 6040592 (2000-03-01), McDaniel et al.
patent: 6043683 (2000-03-01), Bae
patent: 6057586 (2000-05-01), Bawolek et al.
patent: 6118482 (2000-09-01), Clark et al.
patent: 6133563 (2000-10-01), Clark et al.
patent: 6133749 (2000-10-01), Hansen et al.
patent: 6144330 (2000-11-01), Hoffman et al.
patent: 0789459 (1997-08-01), None
S. Dabrel, et al., “Basic ESD and 1/0 Design,” Wiley Interscience, John Wiley and Sons, Inc., New York 1998, pp. 150-171.
L. Clark, “A High-Voltage Output Buffer Fabricated on a 2V CMOS Technology”, Intel Corporation, Chandler, Arizona, 1999, 2 pages.

Affiliated with

Also associated with

Rating

Output buffer for high and low voltage bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Output buffer for high and low voltage bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Output buffer for high and low voltage bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3028684