Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
2000-02-24
2001-06-12
Wamsley, Patrick (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S086000
Reexamination Certificate
active
06246262
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the field of output buffers in high speed applications. In particular, the invention is related to circuitry within the output buffer of a 3.3V Low Voltage Differential Signaling receiver operable to prevent damage when the receiver is exposed to a voltage level above its supply voltage.
BACKGROUND OF THE INVENTION
Consumers are demanding more realistic, visual information in the office and in the home. Their demands are driving the need to move video, 3-D graphics, and photo-realistic image data from camera to personal computers and printers through local access network, phone, and satellite systems to home set top boxes and digital video cam recorders. Low Voltage Differential Signaling (LVDS) provides a solution to this consumer demand in a variety of applications in the areas of personal computing, telecommunications, and consumer/commercial electronics. It is an inexpensive and extremely high performance solution for moving this high speed digital data both very short and very long distances: on a printed circuit board and across fiber or satellite networks. Its low swing, differential signaling technology allows single channel data transmission at hundreds of megabits per second (Mbps). In addition, its low swing and current mode driver outputs create low noise, meeting FCC/CISPR EMI requirements, and provide a very low power consumption across frequency.
There are LVDS standards under two standards organizations: a Scalable Coherent Interface standard (SCI-LVDS) and an American National Standards Institute Telecommunications Industry Association Electronic Industries Association standard (ANSI/TIA/EIA). In an interest of promoting a wider standard, these standards define no specific process technology, medium, or power voltages. This means that LVDS can be implemented in CMOS, GaAs or other applicable technologies, migrating from 5 volts to 3.3 volts to sub-3 volt power supplies, and transmitting over PCB or cable thereby serving a broad range of applications. Thus, a valuable characteristic of LVDS is that the LVDS drivers and receivers do not depend on a specific power supply, such as 5 volts. Therefore, LVDS has an easy migration path to lower supply voltages such as 3.3 volts or even 2.5 volts, while maintaining the same signaling levels and performance.
This same valuable characteristic of drivers and receivers independent of power supply specifications poses a disadvantage in that difficulty arises when there are several receivers of multiple voltages integrated within a LVDS application accessible to one bus. Such is the case as shown in
FIG. 1
where a 3.3V LVDS receiver
16
and 5V LVDS receiver
22
use the same bus
24
within an LVDS application such as a telecommunication router
10
. As discussed, the power supply of each receiver
16
and
22
may be any combination of either 2.5, 3.3, or 5 volts since LVDS technology standards require no specific power supply voltage. The router
10
receives two signals from the drivers
12
and
18
of two switches (not shown). Both LVDS drivers
12
and
18
are coupled to two respective LVDS buses
14
and
20
. At the opposite end of each LVDS bus
14
and
20
, an LVDS receiver is coupled,
16
and
22
, to each respective bus
14
and
20
. The first receiver
16
has a 3.3V power supply and the second receiver
22
has a 5V power supply. Each LVDS receiver
16
and
22
is coupled to a bus
24
within the router
10
and generates current to drive a load attached to the bus
24
. For this particular example, the load is a microprocessor
26
. In operation, when one receiver accesses the bus
24
, the other goes into a high impedance mode disabling itself from the bus
24
. Accordingly, when each receiver
16
and
22
uses the bus
24
, its power supply charges the bus
24
. Thus, when the 5V receiver
22
gains access to the bus
24
, its output buffer (not shown) drives the bus
24
from ground to 5 volts. The first receiver
16
at 3.3V power supply must be able to survive exposure to 5 volts during the high impedance mode without conduction of leakage currents flowing into the internal circuitry of the receiver
16
. In summary, the output buffer of every receiver on the bus must be able to survive exposure to a voltage at least equal to the highest supply voltage of any receiver on the bus in order to prevent the conduction of leakage currents from flowing from the bus to the receiver.
Designing the output buffer of a 3.3 V LVDS receiver
16
using thick oxide 5 volt transistors is an approach towards preventing damage from exposure of higher power supply voltages. LVDS high speed applications, such as 400 Mbps applications, use fabrication processes suitable for high-speed, mixed signal designs. Yet, the implementation of thick oxide transistors in fabrication processes suitable for high-speed digital data has a negative impact on the speed of the receiver. Thus, the implementation of thick oxide transistors is not an acceptable solution.
As illustrated in
FIG. 2
, Davis describes a three-state output buffer circuit having a protection circuit in U.S. Pat. No. 5,455,732, which is hereby incorporated by reference. Davis provides a built-in protection against power-rail corruption by bus-imposed voltages when the buffer is in its high-impedance state. In particular the circuit uses a pseudo-power rail which can be used to adjust the bias on the output transistor's bulk and so to prevent a leakage path from occurring between the output node and a power rail via the output transistor source/bulk junction. NMOS transistor QN
80
is the output pull-down transistor, driven by pull-down-transistor driver transistor QN
60
. Transistor QN
70
is the pull-down transistor disabler. The gate of transistor QP
10
is coupled to the input. QN
10
is coupled in series to QP
10
. QN
50
is coupled in series to QN
10
. QP
20
, QN
20
, QN
40
, QP
50
and QN
70
are all coupled in series with one another in this respective order. The enabling signal EB feeds the gates of transistors QP
50
and QN
70
; while the enabling signal E feeds the gate of transistor QP
20
, QP
30
, and QN
50
. The source of QP
30
is coupled to the circuit LINK+. The function of LINK+ is to enable the high-potential power rail to energize PV
CC
, to be coupled to V
CC
, but only when the voltage of the power rail is higher than that of the pseudo-rail PV
CC
, the rail coupled to the node common to QP
30
and LINK+. Pull-up transistor QP
40
, coupled to the drain of QP
30
, is coupled to the comparison circuit COMP. The output signal lead OUT taken from the node common to transistors QP
40
and QN
80
is coupled to the comparison circuit COMP.
This design, however, incorporates low turn-on threshold voltage transistors, QN
10
, QN
20
and QN
40
, which increase the complexity of design and thus, cost. In addition, during the high impedance mode when the output buffer is disabled from the bus, the voltage applied to the gate of QP
40
is V
CC
minus a threshold voltage of approximately 0.4 to 0.5 volts. Accordingly, a leakage current will exist across this transistor QP
40
when the voltage on the output lead OUT is greater than V
CC
. Thus, this design does not eliminate leakage current completely. In addition, QP
10
is required to be a thick oxide transistor which unfortunately has a negative impact on the speed of the receiver and, thus, is not an acceptable solution for high speed applications such as 400 Mbps applications using the fabrication processes suitable for high-speed, mixed signal designs.
FIG. 3
illustrates a third design approach for implementation of the output buffer in a LVDS receiver using a first and second Schottky diode, S
1
and S
2
to prevent current from conducting into the output buffer. In addition to diodes S
1
and S
2
, the output buffer
100
includes a plurality of p-channel transistors QP
100
, QP
102
and QP
104
, an n-channel transistor QN
100
and a current source I
1
. Transistor QP
100
has a source coupled to a first power supply r
Carvajal Fernando D.
Morgan Mark W.
Brady W. James
Le Don Phu
Mosby April M.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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