Output buffer ESD protection using parasitic SCR protection...

Details Output buffer ESD protection using parasitic SCR protection... Output buffer ESD protection using parasitic SCR protection...

2006-12-26

2006-12-26

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

C257S355000

Reexamination Certificate

active

07154724

ABSTRACT:
An input and output (I/O) circuit with an improved ESD protection is disclosed. The circuit has an output buffer having an NMOS transistor coupled to a PMOS transistor, an ESD protection circuit having a parasitic silicon controlled rectifier (SCR) integrated therein and coupled to the output buffer, and a diode string having a predetermined number of diodes coupled between a source node of the NMOS transistor and ground, wherein a voltage drop across the diode string increases the SCR gate holding voltage, thereby setting an ESD protection holding voltage for the ESD protection circuit.

REFERENCES:
patent: 5473169 (1995-12-01), Ker et al.
patent: 6066879 (2000-05-01), Lee et al.
patent: 6309940 (2001-10-01), Lee
patent: 6521952 (2003-02-01), Ker et al.
patent: 2003/0007301 (2003-01-01), Ker et al.
patent: 2004/0100746 (2004-05-01), Chen et al.

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