Output buffer control circuit that performs high speed operation

Electronic digital logic circuitry – Interface – Current driving

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Details

326 83, 326 17, H03K 190175, H03K 19094

Patent

active

060407158

ABSTRACT:
An output buffer control circuit is provided in which a three-phase (state) level of an output warning can be realized in a short time, which results in increasing the processing speed. The output buffer control circuit uses a predetermined width pulse at the point when the output control signal is changed to low level. The predetermined width pulse is operated with the previous output signal and the resultant signal feeds back to the output terminal. The output buffer control circuit includes a first data latch unit for inverting and latching input data when a latch signal is high level, a data output unit for logically operating an output signal from the first data latch unit based on an output control signal and generating an output data, a second data latch unit for inverting and latching the output signal from the first data latch unit when the output control signal is high level, a signal detector for generating a predetermined width pulse at the point when the output control signal is shifted to low level, and an output terminal pre-reset unit for logically operating the pulse outputted from the signal detector and the output signal from the second data latch unit to pre-reset the output terminal of the data output unit.

REFERENCES:
patent: 5268868 (1993-12-01), Kajigaya et al.
patent: 5300835 (1994-04-01), Assar et al.
patent: 5424983 (1995-06-01), Wojcicki et al.

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