Output buffer control circuit

Electronic digital logic circuitry – Interface – Current driving

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68 81, H03K 190175

Patent

active

061337560

ABSTRACT:
An output buffer control circuit in which an amplitude of a gate input of a MOS transistor for the output's sake is variable by virtue of a program or a mask option, thus there is no electromagnetic interference caused by excessive output current and unnecessary current consumption, is suitable in use for universal integrated circuit. A gate voltage selector circuit selects one out of three voltages (V.sub.DD +.alpha.), V.sub.DD, and (V.sub.DD -.beta.) in accordance with the combination of selection signals S.sub.1, S.sub.2, and S.sub.3. A level conversion circuit performs ON-OFF of a voltage V.sub.1 selected by the gate voltage selector circuit in accordance with a source output signal to be outputted to an outer section with the same cycle as the source output signal, thus communicating it as a gate input to an n-MOS transistor of an output buffer. It is equivalent to that it causes amplitude V.sub.DD of the source output signal to be performed level conversion toward the voltage V.sub.1 which the gate voltage selector circuit selects. It is capable of being obtained the optimum output current because the amplitude V.sub.1 undergoing the level conversion is variable by virtue of the selection signals S.sub.1, S.sub.2, and S.sub.3.

REFERENCES:
patent: 5534801 (1996-07-01), Wu et al.
patent: 6060905 (2000-05-01), Bickford et al.

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