Output buffer circuit with switching speed control circuit

Details Output buffer circuit with switching speed control circuit Output buffer circuit with switching speed control circuit

2001-09-06

2003-06-17

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Accelerating switching

C326S086000, C327S072000

Reexamination Certificate

active

06580285

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2000-382699, filed on Dec. 15, 2000, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices, in particular, including output buffers or input/output buffers.
2. Description of the Related Art
FIG. 16
is a circuit diagram of a conventional output buffer. A buffer
110
with a small transistor size and a low driving capability is a buffer for a high power supply voltage and a buffer
120
with a large transistor size and a high driving capability is a buffer for a low power supply voltage. The level of a power supply voltage is detected, and either the buffer
110
or
120
is selected in accordance with the detection result. The buffer
110
includes P-channel MOS (metal oxide semiconductor) transistors
111
and
112
and N-channel MOS transistors
113
and
114
. The buffer
120
includes P-channel MOS transistors
121
and
122
and N-channel MOS transistors
123
and
124
.
A comparator
102
compares the power supply voltage with a reference voltage generated by a reference voltage generating circuit
101
. An inverter
103
logically inverts the output of the comparator
102
and outputs it to the gates of the transistors
112
and
123
. An inverter
104
logically inverts the output of the inverter
103
and outputs it to the gates of the transistors
113
and
122
. The gates of the transistors
111
,
114
,
121
, and
124
are supplied with an input signal Sin. When the power supply voltage is high, the transistors
112
and
113
are turned on and the transistors
122
and
123
are turned off, so the buffer
110
is selected. Inversely, when the power supply voltage is low, the transistors
122
and
123
are turned on and the transistors
112
and
113
are turned off, so the buffer
120
is selected. The buffer
110
or
120
outputs an output signal Sout. The output signal Sout is a logically inverted signal of the input signal Sin.
The switching speed of a CMOS (complementary metal oxide semiconductor) transistor formed in a semiconductor changes in accordance with process conditions, temperature, and so on, as well as the above-mentioned power supply voltage. Such a change in the switching speed may cause the following problems.
FIG. 4
shows waveforms of the input signal Sin and the output signal Sout when the transistor switching speed is proper. The output signal Sout changes in its waveform with a substantially rectangular shape between the ground potential (0V) and the power supply voltage VDD. When the switching speed is proper, the thus proper output signal Sout is output.
FIG. 17A
shows waveforms of the input signal Sin and the output signal Sout when the transistor switching speed is too low. The rising speed and the falling speed of the output signal Sout are low and the signal falls before it reaches the power supply voltage VDD. As a result, in binary logic consisting of a high level and a low level, the operation of the output signal Sout is delayed, which may cause a malfunction.
FIG. 17B
shows waveforms of the input signal Sin and the output signal Sout when the transistor switching speed is too high. Excessive overshoot and undershoot occur in the output signal Sout at each rising timing and each falling timing, respectively. As a result, the output signal Sout is forced to exceed the threshold level of the logical value, which may cause a malfunction. Moreover, such overshoot and undershoot may cause big noise.
In the output buffers shown in
FIG. 16
, when a switching speed of the transistor has changed due to a change in the power supply voltage, either the buffer
110
or
120
is selected, thereby controlling the transistor switching speed to a proper value. However, no countermeasure can be taken against a change in the transistor switching speed due to a change in process conditions or temperature. As a result, the above-mentioned problem shown in
FIG. 17A
or
17
B arises.
SUMMARY OF THE INVENTION
An object of the present invention is to provide semiconductor devices including input/output buffers or output buffers, which are capable of controlling the transistor switching speed to a proper value even when there is a change in, e.g., process conditions and/or temperature, and to provide control methods thereof.
Another object of the present invention is to provide semiconductor devices capable of detecting the transistor switching speed.
A semiconductor device according to the present invention comprises an output buffer or an input/output buffer including a buffer transistor and a control circuit for changing the size of the buffer transistor. The control circuit changes the size of the buffer transistor on the basis of the switching speed of the buffer transistor or a detection transistor, which speed changes in accordance with process conditions and/or temperature.
The switching speed of the buffer transistor or the detection transistor which changes in accordance with process conditions and/or temperature is detected in advance or in real time, and the size of the buffer transistor is changed in accordance with the detected switching speed. Even when there is a change in process conditions and/or temperature, the switching speed of the buffer transistor can be controlled to a proper value by changing the size of the buffer transistor accordingly.


REFERENCES:
patent: 5334885 (1994-08-01), Morris
patent: 5821783 (1998-10-01), Torimaru et al.
patent: 5864506 (1999-01-01), Arcoleo et al.
patent: 6147521 (2000-11-01), Degoirat et al.
patent: 04321320 (1992-11-01), None

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