Output buffer circuit with logic gate control circuitry

Electronic digital logic circuitry – Interface – Current driving

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Details

326 86, H03K 190175

Patent

active

056614152

ABSTRACT:
The present invention has the object of improving operation speed and operation margin for a GTL driver. An output buffer circuit is of push-pull construction using N-channel MOS transistors MN11 and MN12. An output signal is fed back to pull-up transistor MN11 by way of NOR circuit NOR1, and a low-amplitude, high-speed signal waveform is outputted. The output of this output buffer circuit is inputted to a differential input circuit of another semiconductor integrated circuit. The reference input of the differential input circuit is connected to a reference voltage supply, and the input of the differential input circuit is terminated to the reference voltage supply by terminating resistance. By means of this configuration, the input amplitude of the differential input circuit oscillates with respect to the reference voltage without being affected by the power supply voltage of the output buffer circuit, the power supply voltage of the differential input circuit, or power-supply fluctuations of the reference voltage, thereby broadening the margin against noise.

REFERENCES:
patent: 5057711 (1991-10-01), Lee et al.
patent: 5453705 (1995-09-01), Atallah et al.
patent: 5534791 (1996-07-01), Mattos et al.

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