Output buffer circuit with de-emphasis function

Details Output buffer circuit with de-emphasis function Output buffer circuit with de-emphasis function

2006-08-03

2009-02-03

Cho, James H (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S068000, C327S108000

Reexamination Certificate

active

07486112

ABSTRACT:
Disclosed is an output buffer circuit including main-data output buffers; a de-emphasis output buffer; and a selector that performs switching control in such a way that, based on a control signal indicating whether de-emphasis is to be enabled or disabled, main data is supplied to the de-emphasis output buffer to make the buffer operate as a main-data output buffer when the control signal indicates that de-emphasis is to be disabled, while emphasis data obtained on delaying the main data by the delay circuit is supplied to the de-emphasis output buffer to make the buffer operate as a de-emphasis output buffer when the control signal indicates that de-emphasis is to be enabled.

REFERENCES:
patent: 6897685 (2005-05-01), Sato
patent: 7030657 (2006-04-01), Stojanovic et al.
patent: 7348794 (2008-03-01), Tanaka
patent: 2002-94365 (2002-03-01), None
patent: 2004-88693 (2004-03-01), None

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